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MSP430F5419A: detecting reset reasons

Adam Daluga
Expert 6215 points
Part Number: MSP430F5419A
Other Parts Discussed in Thread: MSP430F5438A

Hello,

I’ve have been looking at detecting reset reasons on an MSP430F5419A.

I am looking at SYSRSTVEC to determine the reset reason.

I found that if SVSLPE bit is enabled, (the BOR default is on) then a watchdog timeout reset results in

SYSRSTIV:0C:SVSL (POR)

 

This makes it difficult for me to determine the cause of the reset.

 

If I clear SVSLPE then I get the correct reset of

SYSRSTIV:16:WDT timeout (PUC)

 

I see the same problem with other reset causes such as

SYSRSTIV:18:WDT password violation (PUC)

SYSRSTIV:14:PMMSWPOR (POR)

 

I am not finding any documentation so would be grateful if you could clarify things and direct me to the correct documents describing my observations.\

THanks,
Adam

  • 0
    Guru 23005 points

    One of the details of SYSRSTIV is that it remembers and returns the reset causes in priority order. So your code needs to read SYSRSTIV until it returns zero to make sure that nothing extra is hanging around.

  • 0 in reply to David Schultz
    TI__Expert 6215 points

    I changed my code to read SYSRSTIV multiple time.

    I can confirm the 2nd read is always zero.

     

    If this helps:

    As part of my startup I am calling the TI library function ConfigMSP430_FastWakeUp();

     

    Some register values:

    PMMCTL0:9602  PMMCTL1:0000  SVSMHCTL:0E12  SVSMLCTL:0202  SVSMIO:0020  PMMIFG:0001  PMMRIE:1100  PM5CTL0:0000 

     Appreciate any help you can provide!

    -Adam

  • 0 in reply to Adam Daluga
    Guru 96315 points

    I'm not familiar with ConfigMSP430_FastWakeUp but from the name I suspect it sets SVSLFP=1 (though I don't see 0x0800 set in SVSMLCTL above).

    Erratum PMM9 [Ref Errata sheet (SLAZ282AB) p. 23] has some interesting things to say about false-positive IFGs coming out of LPM with SVSxFP=1. Is the WDT timeout happening in LPM?

  • 0 in reply to Bruce McKenney
    TI__Mastermind 38665 points

    Hi Adam

    I have try with MSP430F5438A and there is no problem with watch dog reset and check the reset source is 0x16.

    This my test code

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    #include <msp430.h>
    unsigned short reset_;
    int main(void)
    {
    // WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
    P1DIR |= 0x01; // Set P1.0 to output direction
    reset_ = SYSRSTIV;
    while (1) // Test P1.4
    {
    P1OUT ^= 0x01; // Toggle P1.0 using exclusive-OR
    __delay_cycles(100000);
    }
    }
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    I check the reset value by CCS in debug mode. I don't know how do you check the value. 

  • 0 in reply to Gary Gao
    TI__Expert 6215 points

    Hello,

    It has taken me a few days to understand what is happening. I tried your example and it worked correctly. But my code still did not indicate a WDT reset correctly.

    I found the following code demonstrates the problem.

     

        WDTCTL = WDTPW | WDTCNTCL | WDTIS__32K | WDTSSEL__VLO;

        __low_power_mode_3();

        while(1);                                                                   // wait for watchdog. Should not get here because no interrupts enabled.

     

    I discovered it needs both the WDTCTL set and the low power mode. Then I get

    SYSRSTIV:0x0E:-SVSH (POR).

     

    If either is missing I get:

    SYSRSTIV:0x16:-WDT timeout (PUC)

    Thanks for the help!

    Adam

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