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Original question:

MSP430FR5043: Recommended configuration for XPBx External Bias Circuitry

MSP430FR5043: Expected DC offset variation from part to part

Boone
Prodigy 185 points

Part Number: MSP430FR5043

Hello,

I'm wondering what the expected DC Offset UPS/DNS value is across the manufacturing tolerances of these parts?  I ask because we're seeing pretty wide variation from board to board and values that are higher than I had seen in a previous run of boards.  For example, with the PGA set to 25dB I've seen the offset all the way up to -500 on one of the new boards.  Is this to be expected?  Is there a specification for this value?  I don't recall seeing offsets this high on our first batch of boards, so I'm trying to track down what's going on here.

Here's an example of the offset on an ADC sample on one of our new boards below (PGA gain at 25dB).  I've completely disconnected our signal chain from the CH0_IN pin, so it's floating.  The offset seems to be caused internally to the part.

I've done the same thing on a previous version of our board and get very little offset:

Thanks in advance for your help!

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