msp430: dma transfer on timer event blocked if timer event triggers interrupt?

Gauthier ��stervall said:

The problem is that when the interrupts on TACCR0 are enabled, the DMA transfer is not triggered anymore.

Yes, that# show DMA triggers work.

Gauthier ��stervall said:

One solution is to use TACCR1 at a fixed value and run the interrupt on TACCR1 instead

or use the timer overflow interrupt (TAIE/TAIFG), which (in up mode) happens exactly one timer tick after the CCR0 interrupt.

Gauthier ��stervall said:

Where does it say so in the spec (msp430f530x)

Table 9-2 DMA Trigger Operation: "If the TAxCCRx CCIE bit is set, the TAxCCRx CCIFG flag does not trigger a transfer."
Same for the USCI triggers.

It's easy to miss.

The ADC12 behaves differentlky, here the last IFG from a sequence triggers a transfer, and a transfer cannot be triggered by manually setting it. Also, I think, the IE bit may be set and an ISR may be called. And if triggering a DMA by another DMA, things get really complicated.

And I'm not completely sure what 'UCAxTXIFG is automatically reset when the transfer starts" means. I didn't try it other than writing something to TXBUF by DMA (which would clear the IFG bit anyway), but I'm not sure whether the TXIFG bit is cleared (can be cleared at all) if the DMA does not write to TXBUF.

For the CCR0, the IF Gbit is cleared when the ISR is called, so clearign it when teh DMA kicks in instead of an ISR is logical. However, the other CCR units don't clear the IFG bits automatically. It makes sense to clear them once they are honored by a DMA transfer (there is no ISR that could clear them). But I never tested it, though.

Ah, there it is. I felt I recalled seeing something like that somewhere sometime.

Thank you.