TIMER_A PWM generation, changing TACCR (duty cycle) without synchronization

An old design is using TIMER_A PWM (OUTMOD_7) to generate low-bandwidth analog signal. However, TACCR registers are not double-buffered, so because we are generating a variable-duty-cycle PWM signal, care must be taken when changing the duty cycle (TACCR value).

The most suggestions to avoid occasional 100% cycles in the output are to do the TACCR update in the corresponding TACCR interrupt. However, because this is an old design, I wanted to keep the code changes as small a possible; especially I did not want to start adding new interrupt handlers.

I am wondering if OUTMOD_0 could be used to manually force the output signal low after the TACCR value is updated and the TAR value is tested to be larger than the new TACCR. See the code example below:

monitor void set_pwm(unsigned int uValue)
{
#define SAFE_MARGIN 11  // Number of timer cycles used for the comparison and execution of the if block (check from compiled code)

    TA0CCR1 = uValue;
    // Ensure that output is set low even if the value is decreased skipping over the current timer value
    // Do not touch the output if it is close to the wrap-around (avoid too late change)
    if( TA0R >= uValue && TA0R < 0x7FFF /* fixed TA0CCR0 value */ - SAFE_MARGIN ) {
      TA0CCTL1   = (CM_0 | CCIS_2 | OUTMOD_0); // Force output to zero  
      TA0CCTL1   = (CM_0 | CCIS_2 | OUTMOD_7); // Back to PWM mode
    }
}

Description:

• After setting the new TACCR1 value, the timer counter value is checked
• If the timer counter value is same or larger than the new TACCR1 value, the output should be low (may be already low but may be also high if the TACCR1 "skipped" over the timer value)
• To force the output is low even if "skipping" happened, the output mode 0 is activated temporarily with OUT=0. If the output is already low, this has no effect.
• The forced change is not done if the timer is already close to the TACCR0 value, i.e. about to reset and set output to high at any time. Other wise we could set output low "too late" (if the timer wraps to zero just during the if-block).
• [Edit] Note that interrupts must be disabled during this function - otherwise you cannot define suitable SAFE_MARGIN. monitor keyword is for that.

Could this simple solution avoid the extra 100% cycles without any interrupts or waiting loops? In my quick test there are no bumps the filtered analog output signal anymore.