Our circuit board uses an XT1 crystal (32768 Hz) that not stable in the first 600 ms after the DVCC is applied.
Configuration:
ACLK: XT1CLK
SMCLK:DCOCLKDIV With FLL XT1CLK reference clock
MCLK:DCOCLKDIV With FLL XT1CLK reference clock
Clock status:
OFFG = 1
XT1LFOFFG = 1
So during this time within 600 ms (the crystal not stable) the Fail-Safe Operation will do automatically, right?
Does the fail-safe clock always work correctly (100 %)?
Shall we manually configure the FLL reference clock to REFOCLK during this time (start up) and then switch to the XT1 after the crystal stable (600 ms)?