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Original question:

MSP430FR2433: how to improve UART output reliability?

MSP430FR2433: possible/how to prime/warm up UART module to get it ready for transmission upon exit from low power mode?

Zhiyong Li (FT)
Expert 2920 points
Part Number: MSP430FR2433


Tool/software:

Hi,

We have built a sensor around MSP430FR2433. The routine consists of the following steps: 1) System wakes up upon GPIO interrupt; 2) System performs certain measurement related operation, the process takes about several tens to several hundred micro-seconds; 3) System output measurement results via UART after step 2) is complete.

The problem is once in a while the output from step 3) is gibberish/corrupted, adding an arbitrary delay of 100us after step 2) seems able to reduce the frequency when gibberish happens but doesn't completely eliminate gibberish output when deployed in field for long term operation. Alternatively if we wake system via a AT command through UART in step 1) instead of GPIO interrupt, we never observed gibberish output over the course of years of operation.

From the discussion in related thread, the problem seems originated from the fact that SMCLK as clock source of UART needs time to stabilize. I was hoping we can use REFO/ACLK as clock source to avoid such problem. Unfortunately, to my surprise, ACLK cannot be used as clock source on MSP430FR2433.

So my question is, is it possible to somehow prime UART module from step 1)/GPIO ISR? so we don't have to add additional delays after step 2) otherwise it will start to degrade battery life.

Thanks,

ZL

  • 0
    Guru 25175 points

    If the problem is with the stability of SMCLK, then you will have to wait for it to stabilize. Which will depend on the source of SMCLK.

  • 0 in reply to David Schultz
    Expert 2920 points

    Hi Mr. Shultz,

    Thanks for your response. 

    The problem is FLL itself needs additional time to stabilize on top of its clock source (REFO). Adding the following line before UART TX didn't help:

    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked

    Ideally we should just switch to another MCU that actually supports ACLK as clock source for UART, but I will if there is any way we can salvage current design with FR2433.

    Best,

    ZL

  • +1 in reply to Zhiyong Li (FT)
    Guru 25175 points

    I don't know why you left that out before...

    One detail of the FLL is that it isn't enabled in an ISR after waking up from a low power mode. The ISR can do that if needed. If it has a lot to do perhaps.

    If all else fails, try sending a null character to the UART to start. Perhaps before you begin the measurements. 0xFF would be best since that gives a long run before the next start bit.

  • 0 in reply to David Schultz
    Expert 2920 points
    David Schultz said:
    I don't know why you left that out before...

    I left with the hope that we can just switch to ACLK/REFO as clock source which I am surprised to find not supported on FR2433 but FR2422 among a random selection of other FR2xxx MCUs.

    I will go with this solution. Thanks again.

    David Schultz said:
    If all else fails, try sending a null character to the UART to start. Perhaps before you begin the measurements. 0xFF would be best since that gives a long run before the next start bit.

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