MSP430F5308: Timer cannot start right after MC__UP is executed

The timer is going to start. Assuming that ACLK is present of course.

I particularly like how the code has been changed to use ACLK but the comment says SMCLK.

Hi David and Xiaodong, 

From the Timer’s prospect, the setting is similar to my code using timer0, except TA1CCTL0=OUTMOD_4; while in my TA0 code TA0CCTL0=OUTMOD_7;.

But this really doesn’t matter.

Using the sample code you provided, I still can only get TimerA1 activated after running exit(1), and the signature is exactly as same as before.

Because running the sample code needs an external crystal, I changed the clock source to the internal refoclk. This change should not impact the Timer’s performance, right?

#include <msp430.h>

unsigned long sel = 1;

int main(void)

{

  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

  P1DIR |= BIT7|BIT0;                            // P1.7 output

  P1SEL |= BIT7|BIT0;                            // P1.7 option select

if (sel==0) {

    /**********************

     * clk sourc = XT1 external crystal

     ***********************/

  // Configure XT1

  P5SEL |= BIT4|BIT5;                       // Port select XT1

  UCSCTL6 &= ~(XT1OFF);                     // XT1 On

   UCSCTL6 |= XT2OFF;

  UCSCTL6 |= XCAP_3;                        // Internal load cap

  UCSCTL3 = 0;                              // FLL Reference Clock = XT1

  // Loop until XT1,XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle

  do

  {

    UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);

                                            // Clear XT2,XT1,DCO fault flags

    SFRIFG1 &= ~OFIFG;                      // Clear fault flags

  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  UCSCTL6 &= ~(XT1DRIVE_3);                 // Xtal is now stable, reduce drive strength

  UCSCTL4 |= SELA_0;                        // ACLK = LFTX1 (by default)

}

else{

   /**********************

    * clk sourc = refoclk

    ***********************/

  UCSCTL3 = SELREF_2;

  UCSCTL4 =  SELM__DCOCLKDIV| SELS__DCOCLKDIV | SELA__REFOCLK;  //good clock condition

  UCSCTL5 |=DIVA__1 | DIVM__1 | DIVS__2;

  UCSCTL6 = XT1OFF|XT2OFF;

   do

   {

     //UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);

     UCSCTL7 &= ~(XT2OFFG  + DCOFFG + XT1LFOFFG);

                                             // Clear XT2,XT1,DCO fault flags

     SFRIFG1 &= ~OFIFG;                      // Clear fault flags

   }while (SFRIFG1&OFIFG);

}

  // Configure TimerA1

  TA1CCTL0 = OUTMOD_4;                      // CCR0 toggle mode

  TA1CCR0 = 10-1;

  TA1CTL = TASSEL_1 | MC_1 | TACLR;         // ACLK, upmode, clear TAR

  //__bis_SR_register(LPM3_bits);             // Enter LPM3

  __no_operation();                         // For debugger

}

Best regards,

Kim Yue