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Real time clock

Carloalberto Torghele
Intellectual 835 points
Other Parts Discussed in Thread: MSP430F5308

Hi!

I'm using a MSP430F5308.

Is it safe to disable/enable the interrupts (RTCAIE, RTCRDYIE, RTCTEVIE) of the RTC A module while the module is running in calendar mode?

Do i need to stop the RTC A module before enable/disableRTCAIE, RTCRDYIE, RTCTEVIE?

Is it the same for the interrupt flags and AE bits?


I think that the answear is that it's possible to enable/disable interrupts, clear interrupt flags and change the state of the AE bits. But in the user manual there are many warnings about reading and writing real time clock registers while the module it's running. Therefore i'd like to be sure.


Regards,

Carloalberto

  • 0
    Guru 227245 points

    The IE and IFG bits can be written and read independently of the RTC state.

    However, it's better to use the RTCIV register for reading the IFG bits (and writing to it will clear them all), as any CPU access to the IFG register may cause an interrupt event to be lost.

    (if you clear a bit in a register, you read it, modify it and write it back. If the hardware did set a bit in teh meantime, you'll write a value back where this bit wasn't set initially, causing the interrupt to pass unnoticed, as you cleared it the moment it happened)

    For this reason, I don't like that IE and IFG bits are in the same register.

    The warning about reading and modifying RTC registers while the RTC is running, refers to the counter registers. If you read a counter register, or write to it, while the RTC is running, it may be that you're reading one register before and one after a count update.  So you may read 01:59 while the RTC was just counting from 0:59 to 1:00.

    Also, writing to the register in the older RTC (non-A) with the wrong timing could cause the RTC to overwrite the previous register you just wrote. AFAIK this is no longer a problem with the RTC_A.

  • 0 in reply to Jens-Michael Gross
    Intellectual 835 points

    Thank you for your reply.

    At this point I have another doubt.

    MSP430x5xx User Guide said:

    The highest-priority enabled interrupt generates a number in the RTCIV register (see register description).
    This number can be evaluated or added to the program counter (PC) to automatically enter the
    appropriate software routine. Disabled RTC interrupts do not affect the RTCIV value.
    Any access, read or write, of the RTCIV register automatically resets the highest-pending interrupt flag. If
    another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt.
    In addition, all flags can be cleared via software.

    If I clear IE and IFG bits while RTCIV is already set with one interrupt source number, but the interrupt has not been executed yet, is the interrupt still executed even if the corrisponding IE bit is clear?

    Moreover, is RTCIV automatically cleared (or when the IE will get set again the interrupt will be immediately triggered) when you clear the corrisponding IFG bit?

    Just to be more clear I'm gonna write an example:

    // starting point: RTC A running in calendar mode with RTCRDYIE enable.

    __disable_interrupt();

    some code;  // during this code RTCRDYIFG get set and therefore 0x02 is written to RTCIV

    RTCCTL0 = 0; // RTCRDYIFG and RTCRDYIE are cleared. Is it clear also RTCIV?

    __enable_interrupt();

    // is the RTC read ready interrupt executed here?

    some code2;

    RTCCTL0 |= RTCRDYIE; 

    // is the "old" read ready interrupt executed here?

  • 0 in reply to Carloalberto Torghele
    Guru 227245 points

    Carloalberto Torghele said:
    If I clear IE and IFG bits while RTCIV is already set with one interrupt source number, but the interrupt has not been executed yet, is the interrupt still executed even if the corresponding IE bit is clear?

    No. The moment you clear an IE bit, the attached interrupt even is removed from the IV register queue as well as form the pending IRQ list.

    Carloalberto Torghele said:
    Moreover, is RTCIV automatically cleared (or when the IE will get set again the interrupt will be immediately triggered) when you clear the corrisponding IFG bit?

    If you clear the IFG bit, the event is also removed.
    It's a simple realtime AND connection:

    if (IE && IFG) action;

    IE and IFG are the only two memory cells in the whole logic. The rest is done in realtime when required, based on these two values.

    Carloalberto Torghele said:
    // is the RTC read ready interrupt executed here?

    No. It's gone, you cleared it. Some interrupts may be level-triggered (so the IFG bit cannot be cleared as long as the cause for the interrupt is still present), but these are sparse.

    Carloalberto Torghele said:
    // is the "old" read ready interrupt executed here?

    Yu cleared the IFG bit, so it's gone.
    However, if you had only cleared the IE bit, and an interrupt was pending (IFG bit set) but disabled (IE bit clear), it would execute thevery moment you set the IE bit.

    btw: AFAIK, writing to the IV register will clear all IFG bits, whether the corresponding IE bits were set or not.

  • 0 in reply to Jens-Michael Gross
    Intellectual 835 points

    Thank you very much!

    Everything it's clear now!

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