MSP430F5529 ACLK frequency

Hi,

I am using MSP430F5529 in my project,. I want to program ACLK with Ref clock (32.768 Khz). But I see, Aclk is running faster (around 33.4 KHz). Here is my code..any clue. why it is faster and how to correct it?

void Init_SysClock(void)

{

WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

/* Clk & Pll settings */

//UCSCTL4 |= SELA__REFOCLK | SELS__DCOCLK | SELM__DCOCLK; // VLO Clock Sources ACLK

UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO

UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx

UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation

UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz

// (N + 1) * FLLRef = Fdco

// (374 + 1) * 32768 = 12MHz

// Set FLL Div = fDCOCLK/2

__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been

// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

// UG for optimization.

// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle

__delay_cycles(375000);

// Loop until XT1,XT2 & DCO fault flag is cleared

do

{

UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags

SFRIFG1 &= ~OFIFG; // Clear fault flags

}while (SFRIFG1&OFIFG); // Test oscillator fault flag

}