OMAP 3525 SPI - MASTER & MSP430 SPI - SLAVE

Yuvaraj Velumani

Other Parts Discussed in Thread: OMAP3525, MSP430F2419, MSP430G2553

Hi,

I am using MSP430F2419 and OMAP3525 in my design. I was trying to communicate with MSP430 thro' SPI interface, configuring OMAP as master. Iam operating at very low speed (11.7KHz approx), and i have enabled Phase, Clock Polarity, MSB first, 8-bit & Chip select as high to low transition. In-between the signal lines i am using an 1.8V to 3.3V level translator. But iam always receiving data incorrectly value in MSP430 with 2 or 3 bit shift in the result value. only few time it is showing data correctly. i have found there is no problem with the level translator.can any one help e to solve this...

void main(void)
{
volatile unsigned int i;

WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer
if (CALBC1_16MHZ ==0xFF || CALDCO_16MHZ == 0xFF)
{
    while(1);                               // If calibration constants erased
                                            // do not load, trap CPU!!
}
BCSCTL1 = CALBC1_16MHZ;                    // Set DCO to 1MHz
DCOCTL = CALDCO_16MHZ;

//while(!(P3IN&0x08));                      // If clock sig from mstr stays low,
//----------------------------------------------------------------------------//
UCB0CTL1 = UCSWRST;                       // **Put state machine in reset**
UCB0CTL0 |= (UCSYNC+UCMSB+UCCKPL+UCCKPH+UCMODE_2);
P3DIR |= 0x04;                            // it is not yet in SPI mode
P3SEL |= 0x0F;                            // P3.3,2,1 option select
UCB0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**

//----------------------------------------------------------------------------//
IE2 |= (UCB0RXIE+UCB0TXIE); // Enable USCI_B0 TX,RX interrupt

_BIS_SR(GIE);
while(1);
}

// Echo character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCIB0RX_ISR (void)
{
cRxBuff[cRxBuffIndex++] = UCB0RXBUF;
cRxBuffIndex %= RXBUFFLEN;
}
#pragma vector=USCIAB0TX_VECTOR
__interrupt void usciab0tx_isr(void)
{
if ((IFG2 & UCB0TXIFG)) // USCI_B0 TX buffer ready?
UCB0TXBUF = 0xF0;
}

over 16 years ago

0 Harman over 16 years ago

TI__Expert 7845 points

There are no known issue with the SPI as such. In order to rule out whether the issue is with the Master or slave, I would recommend the following:
1. Test the code examples "msp430x261x_uscib0_spi_09.c" & "msp430x261x_uscib0_spi_10.c" from the following zip file:
http://www.ti.com/lit/zip/slac151

2. Use two MSP430's (Master & Slave) to do this test

3. Preferrably do this test on a TI Target board:
http://focus.ti.com/docs/toolsw/folders/print/msp-fet430u64.html

The code examples are available at:
www.ti.com/msp430codeexamples

www.msp430.com

0 Yuvaraj Velumani over 16 years ago in reply to Harman

Intellectual 580 points

Harman,

I tried the above with the TI target board, configuring one spi as master & the other spi as slave, it was working fine.. so i used the same slave code in my hardware to test it.. i found the same prob, but it was clear that it was not reading the LSB bit properly & that bit is getting shifted to msb while im receiving the next byte. Also i found the overrun error occured bit UCOE is enabling on the status register UCB0STAT. As per the data sheet interrupt should be occured when all the data's are received by the shift registers & it has to be moved to UC0RXBUF, in case a case how this UCOE bit is getting enabled????

for ur reference i was transmitting 20 data's form OMAP, say from 0x01 to 0x14, what iam receiving in MSP slave is...

Send Value: 0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14

Received Value: 0x00,0x81,0x01,0x82,0x02,0x83,0x03,0x84,0x04,0x85,0x05,0x86,0x06,0x87,0x07,0x88,0x08,0x89,0x09,0x8A

0 Priya Thanigai over 16 years ago in reply to Yuvaraj Velumani

TI__Mastermind 26380 points

Hello,

I think the problem you are seeing is because the SPI master and slave is out of sync.

This typically happens if the slave SPI is setup and waiting while the master is still configuring the SPI registers.

This may result in level-shifting on the SPI lines even before the master starts sending bytes out. The USCI - SPI slave interprets this as valid data bits causing all following bytes to be shifted by 1 or more bits.

I would recommend:

(1) Uncommenting the line: while(!(P3IN&0x08)); to make sure that the SPI slave is not initialized until the master is ready (since the SPI slave CPU frequency >> SPI data rate you should run through the setup instructions fairly quickly).

(2) Once the SPI master is configured and the SPI lines are idle, reset the SPI slave (via RST pin) before starting to sending data out.

-Priya

0 Charles Kearney over 16 years ago

Prodigy 80 points

Since SPI transmits and receives at the same time you should pick one interrupt to use. It will be faster than servicing two interrupts.

I am having a problem I think is similar to yours. I am talking from a DSP to the MSP430 using SPI with 1MHZ UCLCK. I am sending 9 character commands to the MSP430. Imbetween each character STE goes high. Only the last character is received, with an overrun error. I have found that once STE goes high after a transfer, a minimum amount of time must pass before STE can go low again. The MSP430 must service the interrupt and read RXBUF before STE goes low again for the next transfer.

0 daniel ssss over 14 years ago in reply to Yuvaraj Velumani

Prodigy 55 points

Hello Yuvaraj,

I want to use the MSP as SPI Slave and am experiencing proplbms similar to those you've mentioned in de article above (bit shifting).

I was wondering if you found a solution?

thx in advance

Sincerely

Daniel

0 theophile.alary over 13 years ago in reply to daniel ssss

Prodigy 160 points

Hey everybody,

I experienced trouble for making an OMAP processor (SPI master) to communicate with a MSP430G2553 (SPI slave). Finally, I got a solution that seems to work quite well, even if the code looks ugly !.

Init function :

void spi_init_slave(void){

P1SEL = BIT0 + BIT1 + BIT2 + BIT4; //SS SOMI SIMO MCLK
P1SEL2 = BIT0 + BIT1 + BIT2 + BIT4;
UCA0CTL1 = UCSWRST;
UCA0CTL0 = UCSYNC + UCMSB+UCMODE_2 ;
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCA0RXIE;

}

Interrupt handling :

#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR (void)
{
uint8_t c=UCA0RXBUF;
P1OUT|=BIT5;
if(c==0x22){ // start reading frame
spi_current_byte=0;
while (!(IFG2 & UCA0TXIFG));
UCA0TXBUF = last_pld_frame[spi_current_byte++];
}else if(c==0x55){
while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = 0x55; // Echo (test)
reset=1; // Reset the MCU
}else if(c==0x00){ // continue reading frame
while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = last_pld_frame[spi_current_byte++];
if(spi_current_byte>4)spi_current_byte=0;
}else{
while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = 0xFF; // Unknown cmd ?
}
timer=0;
P1OUT&=~BIT5;
}

#pragma vector=PORT1_VECTOR
__interrupt void Port1 ( void )
{
if(P1IFG & BIT0 ){ // CS -> Low
P1IFG &= ~BIT0;
UCA0CTL1=~UCSWRST; // reset the state of the USCI machine every time CS is asserted low (prevent from byte shifting)
}

}

Note that you'll have to configure the clock polarity on the master, I do not know what is the good configuration, try different one !

Regards,

Theophile Alary

0 Louis Loving over 12 years ago

Prodigy 55 points

I had the same problem using an MSP430 as an SPI slave. I found the thread below very helpful.

http://e2e.ti.com/support/microcontrollers/msp430/f/166/t/214040.aspx

**Attention** This is a public forum

MSP low-power microcontrollers

MSP low-power microcontroller forum

OMAP 3525 SPI - MASTER & MSP430 SPI - SLAVE