Other Parts Discussed in Thread: MSP430F2274
Hi all,
I got a left SHIFT problem on DAta line SDA while using module:USCI_B0 for I2C on MSP430F2274 that is for device address 0xA0 while checked on the scope it is 0x40 hence I need to make an adjustment 0x50
for device adddress 0x64 u need to put 0x32 and (this is not mention in the user guide or MSPFX22x4 related mauals but I got this point from SLAA208 page 3 which says intercaing EEprom using I2c) check it once
also not some errata USCI25 and USCI27 as given below from slaz043g for msp430f2274
USCI25 - Bug description Module: USCI, Function: TXIFG is not reset when NACK is received in I2C mode
Description: When the USCI_B module is configured as an I2C master transmitter the TXIFG is not reset after a NACK is received if the master is configured to send a restart (UCTXSTT = 1 and UCTXSTP = 0).
Workaround: Reset TXIFG in software within the NACKIFG interrupt service routine.
USCI27 - Bug description Module: USCI_B, Function: Timing of USCI interrupts may cause device reset due to automatic clear of an IFG.
When certain USCI I2C interrupt flags (IFG) are set and an automatic flag-clearing event on the I2C bus occurs, the program counter may become corrupted. This happens only when the IFG is cleared within a critical time window (~6 CPU clock cycles) after a USCI interrupt request occurs and before the interrupt servicing is initiated.
The affected interrupts are UCBxTXIFG, UCSTPIFG, UCSTTIFG and UCNACKIFG. The automatic flag-clearing scenarios are described in the following situations:
1) A pending UCBxTXIFG interrupt request is cleared on the falling SCL clock edge following a NACK
2) . 2) A pending UCSTPIFG, UCSTTIFG, or UCNACKIFG interrupt request is cleared by a following Start condition.
Workaround: 1) Polling the affected flags instead of enabling the interrupts. or 2) Ensuring the above mentioned flag-clearing events occur after a time delay of 6 CPU clock cycles has elapsed since the interrupt request occurred and was accepted.
SDA BIT SHIFTing
Also,thegenerationoftheI2CControlByteisdoneinaspecialway.TheMSP430I2CmodulesendsouttheslaveaddressthatisdefinedinthecontrolregisterI2CSA.Notethattheslaveaddressislocatedwithinthecontrolbyteinthebitpositions1to7.ThenumberthatisdefinedintheregisterI2CSAhastobeshiftedonebitpositiontothelefttogettheEEPROMControlByte(Figure3).ForexampleiftheControlByteshouldbe0xA0theslaveaddress(I2CSA)hastobedefinedas0x50.TheR/Wbit,whichisalsolocatedinthecontrolbyte(bit0),ishandledautomaticallybytheselectedtransmitorreceivemode.ThemodeisselectedusingtheI2CTRXbitintheI2CTCTLcontrolregister