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MSP430FG4618 UART does not receive nor transmit

Daniel Franch
Prodigy 90 points
Other Parts Discussed in Thread: MSP430FG4618, MSP430WARE

Hi,

I am currently using an MSP430FG4618 in a project that needed serial communication. I created a project just to test the USART in the UART mode. I think I configured all the registers right, but it did not work. The code is the following: 

/*
* main.c
*/
#include <msp430fg4618.h>

void main(void) {

WDTCTL = WDTPW | WDTHOLD; // Stop watchdog time

P4SEL |= BIT0 + BIT1;
U1CTL |= SWRST;
U1CTL |= CHAR;
U1TCTL |= SSEL0;
U1MCTL = 0x03;
UBR01 = 0x6d;
UBR11 = 0;
ME2 |= UTXE1 + URXE1;
IE2 |= URXIE1 + UTXIE1;
U1CTL &= ~SWRST;

__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
__no_operation(); // For debugger

}

#pragma vector=USART1RX_VECTOR
__interrupt void usart1_rx (void)
{
while (!(IFG1 & UTXIFG1));
TXBUF1 = RXBUF1;
}

I am not using any external clock, only the internal clock. 

After a lot of tests I tried using some MSP430ware example code for this processor. All of them seemed to use an external crystal as clock source. I tried making the changes to use the internal clock only, but I couldn't make even the example code work.

What am I missing?

  • 0
    Guru 227245 points

    Daniel Franch said:
    UBR01 = 0x6d;
    UBR11 = 0;

    Users guide and also the device datasheet (peripheral map) list these two register as U1BR0 and U1BR1. Especially UBR01 looks strage (even if the UART number is appended to the letters, I'd expect it to be UBR10.

    Daniel Franch said:
    ME2 |= UTXE1 + URXE1;
    IE2 |= URXIE1 + UTXIE1;
    U1CTL &= ~SWRST;

    On USCI, the IE bits need to be set after SWRST was reset. I'm not sure for the USART. But the users guide too uses this order in the init description.

  • 0 in reply to Jens-Michael Gross
    Prodigy 90 points

    I did those modifications and it still have not worked. 

    Could it be something related to the external crystal? I have checked the voltage at the pins where they should be connected and XIN is high while XOUT is low. I mean, I'm not using it, but could it cause any interference in what I'm doing?

    Also: could it be something with the hardware instead of just the code? I can't see what I'm missing. Unless the master clock is not 1 MHz in that chip, I can't see how the code is wrong.

  • 0 in reply to Daniel Franch
    Guru 227245 points

    Daniel Franch said:
    Could it be something related to the external crystal?

    Yes, indirectly.

    By default, the PLL is active. This means, the DCO is adjusted towards a multiple of the XT1 crystal frequency. If there is a 32kHz crystal, the DCO will finally end up at 1MHz. If there is no crystal, teh FLL will try to adjust the DCO to a multiple of zero. Which can't be reached, of course. But the DCo will end up at the lowest possible frequency for the currently selected (in your case the default) FN_x. Which is somewhere around 0.3 to 0.65MHz.

    If you don't provide a reference clock (the crystal), you need to

    1) disable the FLL (SCG0 bit in status register) optionally disable XT1 (OSCOFF bit in status register) and
    2)  figure out what DCo setting will be closest to 1MHz. As the same DCo settign leads to different frequencies on different MSPs.

    2x family (which doesn't have an FLL) provides some factory-provided settings for different standard frequencies. 5x family has a fallabck internal reference for its FLLif there is no external one. But 4x series requires a crystal to use teh FLL and get a defined DCO clock frequency without individual calibration.

    All demo codes ass(sic!)ume that a crystal is present.

    Somewhere in the forum is a program that automatically determines the required DCO settings (for storage and later use) based on a temporary reference clock. It was released to restore the 2x family calibration settings in case the were accidentally deleted. But it can be used (with some small changes) for 4x family too.

    Keep in mind that when exiting an LPM, the SCG0 and OSCOFF bits are cleared when using the default macros, re-enabling the FLL.

  • 0 in reply to Jens-Michael Gross
    Prodigy 90 points

    That seems to be exactly the problem. We are using our own board, not a development board. And we are not using a crystal on it. We tried turning off the FLL and the Oscilator as you suggested and we could make the serial work briefly but with the wrong baud rate. But then we got really weird results as the code not being stuck in the while(1) loop. It just goes out of it and back to the beginning of the code again. 

    We didn't find the software that would give us the value we wanted here in the forum and tried just tweaking with the registers.

  • 0 in reply to Daniel Franch
    Guru 46710 points

    Daniel Franch said:
    code not being stuck in the while(1) loop

    What loop? I don't see any in your posted code.

    Daniel Franch said:
    It just goes out of it and back to the beginning of the code again. 

    WDT reset happens?

  • 0 in reply to Ilmars
    Prodigy 90 points

    Sorry. I did that modification along with the other stuff. I read that Low-Power mode could reset the the flags for turning off the oscilator, so I erased the lpm to put a while(1) loop. But I didn't check the watchdog. Completely forgot about that.

  • 0 in reply to Daniel Franch
    Guru 46710 points

    Daniel Franch said:
    But I didn't check the watchdog. Completely forgot about that.

    So now you are happy and everything is fine?

  • 0 in reply to Ilmars
    Prodigy 90 points

    I wish! I still have to go back to the lab and check the Watchdog Timer. And try to figure out how to set the internal clock to 1MHz.

  • 0 in reply to Daniel Franch
    Guru 227245 points

    Daniel Franch said:
    I read that Low-Power mode could reset the the flags for turning off the oscilator,

    Actually, the LPMx_bits defines for exiting LPM contain these bits too, so the standard "convenience" defines cannot be used to exit LPM then.

    About the DCO setting, well, try and error is a possible way too.

    You can output the current MCLK or SMCLK or ACLK on a port pin (secondary pin function, see datasheet). So you can measure what the current DCO speed is.

    Or you generate a capture interrupt by an external signal with, say, 1kHz and count the timer ticks in this interval. Once you get 1000 during one interval, you have the DCO at 1MHz and can store this value.
    Thsi is effectively what the FLL does wiht the crystal.

    Hey, you can even put 32768Hz into XT1 pin and let the FLL adjus tthe DCO. Once it has settled, switch the FLL off and write down the current DCO config. So you're temporarily simulating the crystal (In XT1 bypass mode) without really having one.

  • 0 in reply to Jens-Michael Gross
    Prodigy 90 points

    In the end, we had to do some white-wiring to stick a crystal oscillator in the board. It was way easier than trial-and-error with the DCO. Now everything is working fine. Thank you.

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