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DMA with external trigger

Other Parts Discussed in Thread: MSP430F5529

Hello all community members,

I am using DMA0 channel with edge-sensitive external trigger in my project with MSP430F5529. I have faced problem with repeated block transfer mode. I used the following piece of code to setup DMA0 module :

//************************************************************************************************

unsigned char TX_DATA=0 ;

__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &TX_DATA);        // source addr

__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCB1TXBUF);   // destination addr


DMACTL0 = DMA0TSEL_31;
DMA0SZ = 27;                                                                                                                // block size , number of transforms
DMA0CTL = DMASRCINCR_3 + DMADT_5 + DMAEN ;                                              // increment source addr, repeated BT mode, DMA0 enable


__bis_SR_register(GIE);                                                                                                // enable general interrupts

//***********************************************************************************************

According to the code, it is expected that each rising external trigger , performs a complete block of data transform (27 bytes or 27*8= 216 spi clock cycles).

 But the number of transferred bytes is not equal to 27.

Please see the following figure ; one wrong block transform after an external trigger captured from oscilloscope.The green wave form belongs to external trigger and the pink wave belongs to SPI clock.

Thank you for your help , in advance !!

-Mohammad

 

  • Mohammad Behfar said:
    performs a complete block of data transform (27 bytes or 27*8= 216 spi clock cycles).

    This calculation is wrong. Writing 27 bytes to TXBUF doesn't mean that it takes 216 clock cycles. There is only one trigger. So the DMA doesn't wait for the previous byte being sent before it write the next.

    One transfer takes 2MCLK cycles, so best case (SPICLK == MCLK), the DMA writes 4 bytes to TXBUF while the SPI is shifting out one. 3/4 of your transmission are lost.

    What you can do is to onfigure one DMA channel to move a config byte from memory to the SUCI control register, releasing the USCI from reset. Then another DMA is waiting for the TXIFG bit as trigger and does one transfer each time it is set. Both would be single transfers.

  • Thank you Jens-Michael

    I got your point and solved the problem by setting the SPICLK 4 times faster than MCLK. it seems to work correctly but I still need to validate the transmitted data.

    Regards, 

    Mohammad.

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