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MSP430FR5969 (Wolverine) low power modes problem

Sai Vemprala
Prodigy 170 points
Other Parts Discussed in Thread: MSP430G2553

Hello all,

I have been observing some strange behavior with the Wolverine MSP with regards to its low power sleep modes. If a simple timer is sourced from the SMCLK, which is in turn sourced from the DCO, and the processor is instructed to go to LPM3 or LPM4 (where the DCO needs to be shut down), I see no change in the timer pulses, they still continue. Especially in LPM4, when both the watchdog is stopped and all clock sources are nonexistent, the CPU still continues to operate its TA0/TA1 timers.

Whereas with a MSP430G2553, it works as expected: i.e., the pulses stop once the processor enters LPM4. (or lpm3, as I do not have a crystal) Any suggestions about why this might be happening / how it can be solved will be very helpful. Thank you in advance.

The code that has been used for the timer testing is similar to what has been provided in the TI samples.

WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

 

  // Configure GPIO

  P1DIR |= BIT0 | BIT1;                     // P1.0 and P1.1 output

  P1SEL0 |= BIT0 | BIT1;                    // P1.0 and P1.1 options select

 

  // Disable the GPIO power-on default high-impedance mode to activate

  // previously configured port settings

  PM5CTL0 &= ~LOCKLPM5;

 

  CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers

  CSCTL1 = DCOFSEL_0;                       // Set DCO = 8MHz

  CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;// set ACLK=VLO;SMCLK=DCO

  CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;     // set all dividers

  CSCTL0_H = 0;

 

  // Configure Timer0_A

  TA0CCR0 = 1000-1;                         // PWM Period

  TA0CCTL1 = OUTMOD_7;                      // CCR1 reset/set

  TA0CCR1 = 750;                            // CCR1 PWM duty cycle

  TA0CCTL2 = OUTMOD_7;                      // CCR2 reset/set

  TA0CCR2 = 250;                            // CCR2 PWM duty cycle

  TA0CTL = TASSEL__SMCLK | MC__UP | TACLR;  // SMCLK, up mode, clear TAR

 

  __bis_SR_register(LPM4_bits);             // Enter LPM0

  __no_operation();                         

  • 0
    Guru 227245 points

    Sai Vemprala said:
    the CPU still continues to operate its TA0/TA1 timers.

    The CPU does not 'operate' the timers. The timers are running independently of the CPU, once configured. The CPU may be stopped and the timers will still run as long as they are clocked.

    While entering LPM4 is supposed to stop SMCLK and ACLK (and MCLK), the active timer will still request its clock conditionally, and the default CS config will grant this request, preventing the clock from being shut down. You'll need to clear the REQEN bits in CSCTL6 to prevent the clock request from the timer keeping the clock active. Or you have to stop the timer prior to entering LPM.

    However, what sense does it make to have the timer active and shut down its clock source?

  • 0 in reply to Jens-Michael Gross
    Prodigy 170 points

    Thank you for the explanation. So is this a Wolverine specific feature? Because it didn't happen with the other MCU.

    Also, initially, it was a simple  typo where I wrote LPM4 instead of LPM3, and I was surprised that it still worked. Then out of curiosity, I tried LPM3 without a crystal, and it stil worked.

  • 0 in reply to Sai Vemprala
    Guru 227245 points

    Sai Vemprala said:
    is this a Wolverine specific feature? Because it didn't happen with the other MCU.

    The REQEN bits are a feature of the Power Management Module which was introduced with F5x family. 4x and before don't have it.

    It is unclear (not really covered by the users guides) which modules do a conditional (and therefore deactivatable) and which do an unconditional clock request and when.
    So my information is based on deduction and is not authoritative.

  • 0 in reply to Sai Vemprala
    TI__Guru 74146 points

    Sai Vemprala said:
    Thank you for the explanation. So is this a Wolverine specific feature? Because it didn't happen with the other MCU.

    Clock request enable is a feature that is found on several MSP430 device families, including FR57xx, FR59xx (wolverine), and F5xx/6xx. You just need to check the clock module section of the user's guide for the family that you are using to see if it has this feature.

    The reason that you didn't see it with the G2xx part is that was a 2xx device, which does not have this feature in the clock module.

    You can disable clock request enable on FR59xx by clearing the corresponding bit in the CSCTL6 register. In this case, where you are using SMCLK as your timer source, you would clear SMCLKREQEN if you want SMCLK to be stopped in LPM even if there are active modules requesting this clock (by default SMCLKREQEN = 1 and is enabled). Or you could just stop the timers before entering LPM, as Jens-Michael also suggested, meaning that no modules are requesting SMCLK.

    Regards,

    Katie

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