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SD24B Operation in LPM3 SMclk Stopping

Mike KROON
Prodigy 20 points

I'm using a 430F6779 sampling in LPM3 mode. The convertor is setup to INT once the conversion is complete. Here it will process the data and return to the LPM state. The MCLK is increased by selecting between the DCO CLK and DCOCLKDIV source. Aclk, Mclk, SMclk  are able to be monitored via the IO-Pins

Periodically the timer will cause the system to exit LPM and service the display etc then return to LPM3.

The Issue is that with the JTAG debugger plugged in the system operates as expected, however when the JTAG is removed then the the SMCLK Stops when the LPM3 is entered even though the SD24B Conversion has started. From the reading the SMCLKREQEN should be set by the SD24 allowing the conversion to complete.

Does anyone have any ideas as to what is the difference in the clk operation with the FET connected and removed.

Any other thoughts appreciated

  • 0
    Guru 227245 points

    Mike KROON said:
    Does anyone have any ideas as to what is the difference in the clk operation with the FET connected and removed.

    Depending on configuration, an established FET connection may keep the clocks running (preventing LPM >0)
    However, just idly connecting it (but not launching the debugger on the PC) shouldn't interfere.

    And you're right, the SD24 should keep the clock running as long as it is required (conditional request). But I'm not sure whether the SD24B generates a conditional clock request at all. By design, the SD24 is for continuously running, and not for individual single conversions. That's a main difference between an SAR ADC like the ADC10/12 and a Delta-Sigma ADC like the SD24. And for continuous operation, there is no need to conditionally request a clock - the user should know whether the Sd24 shall run or not - and not deactivate the clock if it is needed.

    BTW, note that modulation of the DCO affects the SD24 precision. Don't use DCOCLK undivided if modulation or FLL are active.

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