CC430F5137: use SMCLK in mode LPM3

I use the SMCLK for the timer TA1 to capture a input signal. The software enters into LPM3 mode repeatedly to wait for interrupts of RF and captured input signals. According to the "table 3-1 Clock Request System and Power Modes" in CC430 User Guide I need to set the bit SMCLKREQEN in register USCTL8 high so that the SMCLK can be active when CC430F5137 is in LPM3 mode. 

I also use the extra low power mode to make CC430F5137 consuming only a few uA current during the LPM3 mode. 

I do not see the register USCTL8 in the cc430f5137.h file. Could you please tell if I should set  the bit SMCLKREQEN in register USCTL8 high and how.

Below are part of my software:

TA1CTL = TASSEL_2 + MC_2 + TACLR; // SMCLK, contmode, clear TAR

TA1CCTL0 = CM1 & msk_0 | // CM[1:0] = 10 => capture on rising edge
CM0 & msk_1 |
CCIS1 & msk_0 | // CCIS[1:0] = 00 => select input CCI0A (pin)
CCIS0 & msk_0 |
// SCS = 1 => synchronize capture to clock (recommended)
SCS & msk_0 |
// SCCI is synchronized CCI input, don't care here
SCCI & msk_0 |
CAP & msk_1 | // CAP = 1 => capture mode
OUTMOD2 & msk_0 | // OUTMOD[2:0] = 000 => compare output = OUT bit
OUTMOD1 & msk_0 |
OUTMOD0 & msk_0 |
CCIE & msk_0 | // CCIE = 0 => CC interrupts initially disabled
CCI & msk_0 | // CCI is unsynchronized CC input, read only
// OUT = 0 => CC output = 0 when OUTMOD[2:0] = 000
OUT & msk_0 |
COV & msk_0 | // COV = 0 => clear capture overflow flag
CCIFG & msk_0; // CCIFG = 0 => clear CC interrupt flag
WiredRx_State = 0; // state 0 => wait to capture for first rising edge

TA1CCR0 =0;
TA1CCTL0 &= ~CCIFG;
TA1CCTL0 |= CCIE; // enable interrupt for first start bit rising edge

..........

//=====================================================
// MAIN LOOP
//=====================================================
while (1)
{
CLRWDT_16s

//make VLO (10khz) as ACLK's clock source
UCSCTL4 = SELA__VLOCLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

....

Strobe(RF_SIDLE);
Strobe(RF_SPWD); //turn off RF

WDTCTL =WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL_2+WDTIS1; //1/16s
SFRIE1 |= WDTIE; // Enable WDT interrupt
__bis_SR_register(LPM3_bits + GIE); //enter LPM3 and re-enable interrupts
// CPU SLEEPS HERE!
__delay_cycles (800ul); //waiting
SFRIE1 &= ~WDTIE; // disable WDT interrupt
//ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default)
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;
//delay_cycles(x) is stopping in the code and waiting for x MCLK cycles

....

}