l3g4200 i2c msp430f2618 how??

Question 1 is related to the l3g4300 internal protocol. Its device datasheet should tell you.

Q2: the I2C start byte is composed of a 7 bit address and a trailing R/W bit.
The F2618 USCI takes the 7 bit slave address (right-justified, so 0 to 0x7f) in its slave address register, while the R/W bit is automatically added based on the (inverted) UCTR bit that defines the transaction direction.

When you set the TXSTT bit, then the USCI will generate a start condition, assemble the start byte form UCTR and slave address, and send it too. Don't send the slave address yourself. (well, in your read function, writing to TXBUF is a NOP anyway, as UCTR is clear)

There are nice diagrams in the users guide, explaining what happens when, and where you have to act and what is done automatically.

Q3: SR? Slave Ready? Start Reading? Spill Rice?
If this is a separate signal line, then you can connect it to a GPIO port of the MSP and handle it using standard GPIO port operations.

In your code, instead of checking the TXIFG and RXIFG status bits of the USCI hardware, you check for an external signal on P3. For what purpose? What does this signal do?
It also makes no sense reading RXBUF and setting UCTXNACK before the start byte has been sent. Again, see the diagrams in the users guide.