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Question on Compute through Power Loss SRAM usage

Lucas Cox
Other Parts Discussed in Thread: TIDM-FRAM-CTPL

I just stumbled across the Compute Through Power Loss library (CTPL http://www.ti.com/tool/TIDM-FRAM-CTPL ), and am quite excited about using it in future projects. I just have one question about it.

Does the modified linker command required for use of CTPL bypass the onboard SRAM and store all local variables in FRAM? Or, does CTPL simply copy all of the SRAM into FRAM on LPM entry and then restore back into SRAM once it is awoken from LPM3.5/4.5?

*If* the linker command does bypass onboard RAM, it would be cool to add the option to reserve a section of FRAM (2K in the case of the FR5969) for copying RAM and then restore that 2K. Yes, this would add time to shutdown/startup after LPM3.5/4.5, but the convenience of not having to deal with the wait-state generator would be worth it to me.

  • 0
    TI__Intellectual 1930 points

    Hi Lucas,

    You are correct, the included linker files place all data into FRAM with the exception of the stack which remains in SRAM (and is copied to FRAM before LPM). This unfortunately mean that the majority of SRAM is unused and it's definitely a limitation of the current CTPL implementation. With that said we already have plans for an update to the utility including more peripherals and the option to place variables into SRAM and copy to FRAM before LPM, exactly like you're describing. I don't have any details on exactly when this update will be available but be sure to keep an eye out for it over the next few months!

    Regards,

    Brent Peterson

  • 0 in reply to Brent Peterson
    Brent,

    Thank you for the quick answer! I'll be looking out for the next update.

    Thanks again,
    -Lucas
  • 0 in reply to Brent Peterson

    Hey Brent (or any other TI engineer who might know),

    It's been several months, so I figured I'd check: Any update on the status of CTPL? 

    Thanks,

    Lucas

  • 0 in reply to Lucas Cox
    TI__Intellectual 1930 points

    Hi Lucas,

    This feature was added in the last release of FRAM Utilities, version 2.00.

    You can now enable saving of SRAM contents by defining CTPL_RAM_SIZE. I attached a modified version of the ctpl_ex1_gpio_lpm45 example that uses the default linker configuration file with data placed in SRAM and CTPL_RAM_SIZE=2 defined in the compiler settings. The example has been modified to only blink the LED if a global flag stored in RAM is correctly restored. With CTPL_RAM_SIZE=2 defined the LED blinks as expected, removing the define causes the program to exit and not blink the LED.

    Regards,

    Brent Peterson

    ctpl_ex1_gpio_lpm45_msp-exp430fr5994_RAM.zip

  • 0 in reply to Brent Peterson

    Thanks for the update, Brent. This will be extremely useful for me.

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