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Hello everyone
I am working on a project which needs ADC works in max frequency.
I configure ADC work with DMA.
ADC Setting:
clk: 25M using DCO
mode: repeat-single-channel and automatic mode
hold time : 8 cycles
conversion time: 16 cycles
DMA setting:
work in PINGPONG MODE, transfer 256 data each time, data length is 16 bits, triggered by ADC14
In the DMA interrupt handler, i will toggle a gpio to measure duration of 2 DMA transfer.
I got the result below. It seems that it takes ADC14 265us to generate 256 samples and not expected 256us.
Any comments to my experiment?
Thank you.
Hi!
It seems you are doing everything ok unless you made some unexpected software overhead in the DMA isr. If possible, just show DMA ISR and other code which possibly can interfere with timing of the test.
First you shall check that your clock frequency indeed is 25MHz. Route clock to corresponding pin and measure frequency. Then you shall chek that everything about ADC configuration is ok.
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