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I have selected ACLK as clock input for Timer A (TASSEL=1).The two clock dividers of Timer A are configured to divide ACLK by 64.
With this configuration I would expect Timer A is clocked by 32768 Hz / 64 = 512 Hz.
To prove this I start the timer A and wait 60 s.
After this wait time, the TAxR is always about 35210.
This means the clock of Timer A is not 512 Hz but 35210 / 60 s = 587 Hz.
So ACLK is 587 HZ * 64 = 37568 Hz (instead of 32768)
What can be the reason for this?
Yes, you are right! This was the missing part.
Now the ACLK is exactly 32768 Hz.
Thanks a lot for your help!
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