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Capturing data from external parallel ADC with DMA transfer?

k1mgy
Expert 1680 points
Other Parts Discussed in Thread: MSP430F6736, ADS7882

MSP430F6736 (actually, any MSP430F5/6 with DMA)
TI ADS7882 12 bit ADC with parallel interface

Our application requires very fast data transfer from the external ADS7882.  There are 12 data lines (12 bit ADC) and 7 other lines for control/status.  The ADS7882 will indicate when data is ready via a hardware line.  Ideally, I'd like this hardware line to cause the MSP430 to read the data across 16 GPIO lines in a single DMA transfer.

It appears that the MSP430 DMA is only for internal peripherals, but if this is possible I'd like some guidance as to how we might go about it.

Note that we need 1.5 to 3 MB/Sec for our ADC.  Can't use internal ADC for the MSP430 as it's not fast enough.

  • 0
    Guru 297970 points
    You could use the DMA to copy a 16-bit word from some port input register to memory.

    (But what is the CPU going to do with the data?)
  • 0
    Guru 34453 points
    Yes, you can do this. On similar way is working my logic analyzer.
    forum.43oh.com/.../
  • 0 in reply to Clemens Ladisch
    Expert 1680 points 
    But what is the CPU going to do with the data?

    It will process it in a batch during periods between taking data from the ADC.

    What do you mean by "some port input register"? 

    My ADC has a 12 bit (13 I/O lines) output.  Ideally I'd like to define a 16 bit-wide "register" based on a selection of GPIO attached to the ADC and then have the ADC signal the DMA to read it and transfer to memory.

  • 0 in reply to k1mgy
    Guru 34453 points

    For example if porta A (16 bits) is used as input...

    #define    Dma0SrcAdr    00512h
    #define    Dma0DstAdr    00516h

            mov.w #PAIN, R15

            mova R15, &Dma0SrcAdr

            mov.w #BUFBEGIN, R15

            mova R15, &Dma0DstAdr

            mov.w #SIZE, &DMA0SZ

    and triggering with...

            mov.w #(DMADT_1 + DMADSTINCR_3 + DMASWDW + DMAEN + DMAREQ), &DMA0CTL

    One line (from PAIN) can be used for ADC data ready, so all not valid (tested by data ready PIN) collected samples with DMA can be removed on micro side.

  • 0
    Mastermind 9045 points

    If MSP430 is running at 20MHz, there are only 20/3=6.x instruction cycles to process one ADC sample in average. I don't think MSP430 is fast enough unless the signal processing is very very simple. You probably need a faster CPU.

  • 0 in reply to Robert Chen
    Guru 11940 points
    As I understood, the OP wants to sample intermittently, and then process the samples in a batch-manner.
    But I believe your objection is true - six instructions might not even suffice to fetch the ADC value and store it.
  • 0 in reply to f. m.
    Expert 1680 points
    At 20MHz and 6 cycles for a transfer this allows at full bore 100 samples within a 5.0 microsecond sampling period. We need 1/10th of that, so the DMA should be fine. We're using this CPU to supervise the ADC, then store and move the data off to another CPU which does the signal processing. I think that within these constraints we'll be A-OK.

    Fortunately we don't need to run the ADC at its full 3MS/Sec rate! More likely we'll be hovering at less than half that...

    Thanks for the DMA example. The user guide was a bit difficult to decipher on DMA from a GPIO port.
  • 0 in reply to k1mgy
    Guru 11940 points

    At 20MHz and 6 cycles for a transfer this allows at full bore 100 samples within a 5.0 microsecond sampling period. We need 1/10th of that, so the DMA should be fine. We're using this CPU to supervise the ADC, then store and move the data off to another CPU which does the signal processing. I think that within these constraints we'll be A-OK.

    Not sure if we talk about the same.

    As I understood Robert's comment, the core requires 3 clock cycles per instruction. For 20MHz core clock, that amounts to only 6 (machine) instructions to process each ADC sample. Coming from the Cortex M world, I don't know the MSP430 core in detail - better check for yourself.

    Other Cortex M cores (from other vendors) have multiple ADC units which can run in a synchronized/interlocked fashion, with up to 2 .. 8 MSps. They are, however, not "low-power".

  • 0 in reply to f. m.
    Guru 34453 points

    MSP430 DMA can copy each 16-bit word from port to RAM with auto increment of target address in 2 CPU cycles (with stopped CPU)

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