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msp430g2553 spi clock phase

Other Parts Discussed in Thread: MSP430G2553

Hi, I'm using two launchpads of MSP430G2553 to test the SPI mode. One works as master, the other slave, the SIMO and SOMI are connected. The master sends 0,1,2,3... to the slave, and then the slave sends back the character. So the number sent back by the slave will always be 1 less than the number sent by the master.

If UCCKPH is 0 for both master and slave, which means that the data will be shifted out at the first edge of the clock and sampled to RX at the opposite edge, the data transmit will be properly working.

But when UCCKPH=1 for both master and slave, the data transmit cannot work well. The data sent by the slave will be delayed one clock to the data sent by the master. And then the data read by the master will be wrong.

So if I want to settle UCCKPH=1, how can the SPI work properly?

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