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I am looking at SYSRSTIV to determine the reset reason. In my test application I stop servicing the watchdog after 100 seconds.
I get the reset value of: 16h = WDT time out (PUC)
If I now call the TI library functions listed below and don't service the watchdog the reset reason changes to:
0Ch = SVSL (POR)
I am trying to understand why the reset reason is changing.
void ConfigMSP430()
{
//SVS Low side is turned off
PMM_disableSvsL(__MSP430_BASEADDRESS_PMM__);
//Monitor low side is turned off
PMM_disableSvmL(__MSP430_BASEADDRESS_PMM__);
//Monitor high side is turned off
PMM_disableSvmH(__MSP430_BASEADDRESS_PMM__);
//SVS High side is turned on
PMM_enableSvsH(__MSP430_BASEADDRESS_PMM__);
//Enable POR on SVS Event
PMM_enableSvsHReset(__MSP430_BASEADDRESS_PMM__);
//SVS high side Full perf mode,
PMM_SvsHEnabledInLPMFullPerf(__MSP430_BASEADDRESS_PMM__);
//stays on in LPM3,enhanced protect
//Wait until high side, low side settled
while ( 0 == PMM_getInterruptStatus(__MSP430_BASEADDRESS_PMM__,
SVSMLDLYIFG + SVSMHDLYIFG )
) ;
PMM_clearPMMIFGS(__MSP430_BASEADDRESS_PMM__);
}
Hi Stephen,
There is a possibility you are experiencing a known erratum PMM9. Please take a look through the MSP430F5510 Device Erratasheet and try the workarounds. There are also several E2E posts concerning this issue as well:
MSP430F5528 SVS Resets - MSP low-power microcontroller forum - MSP low-power microcontrollers - TI E2E...
TI MSP430 5522 can a watchdog timeout cause SVSL and SVSH POR - MSP low-power microcontroller forum ...
Please take a look through these and let me know if the workarounds solve the issue. In the meantime, I'll try recreating the issue on my end.
Best regards,
Caleb Overbay
Hi Stephen,
A quick update:
I was able to recreate the issue with the code you've posted above. I then tried the suggested workarounds for PMM9 and no oonger observed the SVSL (POR) in the SYSRSTIV register.
Best regards,
Caleb Overbay
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