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msp430fw423: Changing TSM starting period in ScanIF

Piotr Romaniuk
Expert 2830 points
Part Number: MSP430FW423

Hi,

This question regards to ScanIF.

I need to change a period of starting TSM on the fly.
I am doing this by reprogramming the divider of ACLK clock (in SIFCTL4.SIFDIV3A / 3B).
Unfortunatelly I observe that switch from SIFDIV3_162 | SIFDIV2_2 to SIFDIV3_18 | SIFDIV2_2 takes about 5ms. This is delay before first cycle of the TSM with new period.

Is it possible to make this delay shorter? What it depends on?

Regards,
Piotr

  • 0
    TI__Mastermind 49692 points

    Hello Piotr,

    According to page 902 in the MSPx4xx User's Guide, the TSM automatically starts and re-starts periodically based on a divided ACLK start signal selected with the SIFDIV2x bits, the SIFDIV3Ax and SIFDIV3Bx bits when SIFTSMRP = 0. For example, if SIFDIV3A and SIFDIV3B are configured to 270 ACLK cycles, then the TSM automatically starts every 270 ACLK cycles. When SIFTSMRP = 1 the TSM re−starts immediately with the SIFTSM0 state at the end of the previous sequence i.e. with the next ACLK cycle after encountering a state with SIFSTOP = 1. The SIFIFG2 interrupt flag is set when the TSM starts.

    The SIFDIV3Ax and SIFDIV3Bx bits may be updated anytime during operation. When updated, the current TSM sequence will continue with the old settings until the last state of the sequence completes. The new settings will take affect at the start of the next sequence.

    On page 933 in the MSPx4xx User's Guide, you will find a table with possible delays in ACLK cycles ranging from 2 cycles to 450 cycles.

    Does this make sense?

    Regards,

    James

    MSP Customer Applications

  • 0 in reply to James Evans
    Expert 2830 points
    Hi James,

    Thank you for your response. The problem is different.
    In my program I need two modes of operation:
    a) "regural" mode - slow sampling (10ms), mainly used in my device work,
    b) "fast" mode - (300us), used rarely.
    I have no problem in correct setting the registers for these two periods.
    The issue is when I switch from one mode to another. I observe there long delay (about 5ms) that ruins my time constrains.
    That is why I would like to understand what is an origin of this delay and how it can I minimized.

    Regards,
    Piotr
  • 0 in reply to Piotr Romaniuk
    Prodigy 80 points

    Same problem here!

    I need to perform auto calibration of SacnIF using TCI method. For that I increase frequency of SIF from 50Hz to 1000Hz. So At begining I have TSM cycles every 20ms. Then right after SIFIFG3 interrupt flag is set and interrupt is triggered I setup new frequency. BUT, next cycle is triggered after 10ms and then rest of cycles are triggered every 1ms.

    It looks like ScanIF is sleeping during cycles, but wakes up every half cycle to check for test cycle (it is also injected in the middle of period). And in this point it switches the frequency. Sadly, I couldn't reduce this half cycle dead time when freq is changed.

    Regards.

  • 0 in reply to Piotr Romaniuk
    TI__Mastermind 49692 points
    Hello Piotr,

    Are you setting SIFTSMRP = 1 in your code? This immediately restarts the TSM at SIFTSM0 state after encountering the last state with SIFSTOP = 1. However, the TSM restart occurs on the next ACLK cycle, which causes a small delay (~1/32768Hz) but would be much less that the 5ms that you're observing.

    If you want to measure the delay between the SIFTSMx state with a stop bit and the start of the TSM, look at the time between the SIFIFG1 interrupt flag (TSM stops) and SIFIFG2 (TSM starts).

    Regards,

    James

    MSP Customer Applications
  • 0 in reply to James Evans
    Expert 2830 points
    Hi James,

    In my application SIFCTL5.SIFTSMRP = 0, because I need periodic measurement. The frequency I controll by setting SIFCTL4:
    1) in 'regural mode' it equals SIFDIV3_162 | SIFDIV2_2,
    2) in 'fast mode' I change it to SIFDIV3_18 | SIFDIV2_2.

    When I need to switch to 'fast mode' I wait for SIFIFG1 interrupt(TSM Stop), I reset it and change SIFCTL4 to [2].

    Regards,
    Piotr
  • 0 in reply to Piotr Romaniuk
    TI__Mastermind 49692 points
    Hello Piotr,

    This makes sense. Keep in mind that the SIFDIV3Ax and SIFDIV3Bx bits may be updated anytime during operation. When updated, the current TSM sequence will continue with the old settings until the last state of the sequence completes. The new settings will take affect at the start of the next sequence.

    In your code, when you want to switch from regular mode to fast mode, perhaps you could change the SIFDIV3Ax/Bx bits during the last regular mode sequence. Do the same thing for the fast mode when you want to switch back to regular mode. Now, the User's Guide doesn't specify that the SIFDIV2 bits can be changed during operation, but since they don't need changed, this should work.

    The 5ms delay is most likey the time spent resetting the TSM and changing SIFCTL4.

    Regards,

    James

    MSP Customer Applications
  • 0 in reply to James Evans
    Expert 2830 points

    James Evans said:
    Hello Piotr,

    This makes sense. Keep in mind that the SIFDIV3Ax and SIFDIV3Bx bits may be updated anytime during operation. When updated, the current TSM sequence will continue with the old settings until the last state of the sequence completes. The new settings will take affect at the start of the next sequence.

    Hi James,

    I change SIFDIV3xx after TSM is stopped, i.e. last command is executed and interrupt is generated. I do not understand why the update of these registers is not effective immediately.

    Regards,
    Piotr

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