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Hi, I am trying to read A1 and A2 ADC channels with interrupts enabled. For some reason, I get no analog data. Below is my ADC code:
//Initialize ADC A1 and A2 void adc_int(void){ ADC12CTL0 = ADC12SHT02 + ADC12ON + ADC12MSC; ADC12CTL1 = ADC12SHP; ADC12IE = ADC12IE0 + ADC12IE1 + ADC12IE2; __enable_interrupt(); ADC12CTL0 |= ADC12ENC; P6SEL |= 0x06; ADC12IFG &= ~BIT0; ADC12IFG &= ~BIT1; ADC12IFG &= ~BIT2; ADC12IFG &= ~BIT3; ADC12IFG &= ~BIT4; ADC12IFG &= ~BIT5; ADC12IFG &= ~BIT6; ADC12IFG &= ~BIT7; ADC12IFG &= ~BIT8; ADC12IFG &= ~BIT9; ADC12IFG &= ~BITA; ADC12IFG &= ~BITB; ADC12IFG &= ~BITC; ADC12IFG &= ~BITD; ADC12IFG &= ~BITE; ADC12IFG &= ~BITF; } // Main while (1) { ADC12CTL2 |= ADC12SC; // Start sampling/conversion __no_operation(); if((ADC12IE &= ADC12IE0) == 0)//Reenable interrupts ADC12IE = ADC12IE0 + ADC12IE1 + ADC12IE2; } //Interrupt #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) #pragma vector = ADC12_VECTOR __interrupt void ADC12_ISR(void) #elif defined(__GNUC__) void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12_ISR (void) #else #error Compiler not supported! #endif { switch(__even_in_range(ADC12IV,34)) {//Reading the ADC12MEMx register clears the respective interrupt flag case 0: USBCDC_sendDataInBackground(messageADC1, 15, CDC0_INTFNUM, 1000); break; // Vector 0: No interrupt case 2: USBCDC_sendDataInBackground(messageADC2, 15, CDC0_INTFNUM, 1000);//Print Message break; // Vector 2: ADC overflow case 4: USBCDC_sendDataInBackground(messageADC3, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); break; // Vector 4: ADC timing overflow case 6: // Vector 6: ADC12IFG0 ADC12IFG &= ~ADC12IFG0; ADC12IE &= ~ADC12IE0; USBCDC_sendDataInBackground(messageADC4, 15, CDC0_INTFNUM, 1000); __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; case 8: // Set the flag when sample is ready BatStat = ADC12MEM1; ADC12IFG &= ~ADC12IFG1; ADC12IE &= ~ADC12IE1; USBCDC_sendDataInBackground(messageADC5, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 8: ADC12IFG1 case 10: ADCflag = 1; // Set the flag when sample is ready VSET = ADC12MEM2; ADC12IFG &= ~ADC12IFG2; ADC12IE &= ~ADC12IE2; USBCDC_sendDataInBackground(messageADC6, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 10: ADC12IFG2 case 12: ADC12IFG &= ~ADC12IFG3; ADC12IE &= ~ADC12IE3; USBCDC_sendDataInBackground(messageADC7, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 12: ADC12IFG3 case 14: ADC12IFG &= ~BIT4; USBCDC_sendDataInBackground(messageADC8, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 14: ADC12IFG4 case 16: ADC12IFG &= ~BIT5; USBCDC_sendDataInBackground(messageADC9, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 16: ADC12IFG5 case 18: //ADCflag = 1; // Set the flag when sample is ready //__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU ADC12IFG &= ~BIT6; USBCDC_sendDataInBackground(messageADC10, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 18: ADC12IFG6 case 20: ADC12IFG &= ~BIT7; USBCDC_sendDataInBackground(messageADC11, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 20: ADC12IFG7 case 22: ADC12IFG &= ~BIT8; USBCDC_sendDataInBackground(messageADC12, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 22: ADC12IFG8 case 24: ADC12IFG &= ~BIT9; USBCDC_sendDataInBackground(messageADC13, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 24: ADC12IFG9 case 26: ADC12IFG &= ~BITA; USBCDC_sendDataInBackground(messageADC14, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE setbreak; // Vector 26: ADC12IFG10 case 28: ADC12IFG &= ~BITB; USBCDC_sendDataInBackground(messageADC15, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 28: ADC12IFG11 case 30: ADC12IFG &= ~BITC; USBCDC_sendDataInBackground(messageADC16, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 30: ADC12IFG12 case 32: ADC12IFG &= ~BITD; USBCDC_sendDataInBackground(messageADC17, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 32: ADC12IFG13 case 34: ADC12IFG &= ~BITE; USBCDC_sendDataInBackground(messageADC18, 15, CDC0_INTFNUM, 1000);//Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE set break; // Vector 34: ADC12IFG14 default: ADCflag = 1; USBCDC_sendDataInBackground(messageADC, 15, CDC0_INTFNUM, 1000);///Print Message __bic_SR_register_on_exit(LPM0_bits + GIE); // Exit LPM0 with GIE cleared (disabled) break; } }
the ADC12MCTLx registers will all be set for A0 unless/until you change them
see also the usage eof the ADC12CONSEQ bits in register ADC12CTL1
also, AD12SC bit is NOT in ADC12CTL2
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