MSP432P401R: MSP432 as a slave spi communication problem

Part Number: MSP432P401R

Hello everyone,

     I am trying to communicate between  MSP432 (as Slave) and TMS320F28027-C2000 launchpad(as  Master) via SPI.

- SPI slave (msp432)  talks to SPI master(f28027) using 4-wire mode with slave select enabled. in the code, master transmit 0x81 data to slave. If Data received from master is 0x81 then slave will transmit 0x88 to master else transmit 0xAA.

    when i debug the code msp432 can not receive the data 0x81 instead of it receive dummy data 0xFF and transmitt 0xFF also.when i pause the code data transmit in buffer is 0xAA is right because condition is not satisfied. But on oscilloscope, it shows 0xFF on MISO line.

I am attaching a code for reference:-

MSP432P401R(slave):-

static uint8_t RXDATA = 0;

void InitSPI(void)
{
P10->SEL0 |= BIT0 | BIT1 | BIT2 | BIT3; // set 4-SPI pin as second function

EUSCI_B3->CTLW0 |= EUSCI_B_CTLW0_SWRST; // Put state machine in reset
EUSCI_B3->CTLW0 = EUSCI_B_CTLW0_SWRST |
EUSCI_B_CTLW0_SYNC | // Synchronous mode
EUSCI_B_CTLW0_CKPL | // Clock polarity high
EUSCI_B_CTLW0_MSB | // MSB first
EUSCI_B_CTLW0_MODE_1 | // 4-pin SPI mode
EUSCI_B_CTLW0_STEM ; // STE mode select
EUSCI_B3->CTLW0 |= EUSCI_B_CTLW0_SSEL__SMCLK; // ACLK
EUSCI_B3->BRW = 0x01; // /2,fBitClock = fBRCLK/(UCBRx+1).
EUSCI_B3->CTLW0 &= ~EUSCI_B_CTLW0_SWRST;// Initialize USCI state machine
EUSCI_B3->IE |= EUSCI_B_IE_RXIE; // Enable USCI_B3 RX interrupt

// Enable eUSCI_B3 interrupt in NVIC module
NVIC->ISER[0] = 1 << ((EUSCIB3_IRQn) & 31);

}

// SPI interrupt service routine
void EUSCIB3_IRQHandler(void)
{
if (EUSCI_B3->IFG & EUSCI_B_IFG_RXIFG)
{
// USCI_B0 TX buffer ready?
while (!(EUSCI_B3->IFG & EUSCI_B_IFG_TXIFG));

// Echo received data
RXDATA=EUSCI_B3->RXBUF;

if (RXDATA==0x81)
{
// USCI_B0 TX buffer ready?
while (!(EUSCI_B3->IFG & EUSCI_B_IFG_TXIFG));

// Echo received data
EUSCI_B3->TXBUF = 0x88;
}
else
{
// USCI_B0 TX buffer ready?
while (!(EUSCI_B3->IFG & EUSCI_B_IFG_TXIFG));

// Echo received data
EUSCI_B3->TXBUF =0xAA;
}
// Clear the receive interrupt flag
EUSCI_B3->IFG &= ~EUSCI_B_IFG_RXIFG;

}
}

F28027(Master):-