MSP430F6736A: SD24, ADC10 and DMA - Repeated - Sequence of channels

Mehmet Fide

Prodigy 80 points

Part Number: MSP430F6736A

Hi,

We have an application that should use 3 channels of SD24 and 15 channels of ADC10 synchronously.

The MSP430 that we use has a special trigger module to trigger ADC10 at the end of every SD24 conversions.

And I configured ADC10 in "repeated-sequence of channels - ADC10CONSEQ_3" mode with auto next conv (MSC set)

And finally, I configured DMA in repeating single transfer mode.

I expect that;

1. SD24 will trigger ADC10.

2. With this single trigger, ADC10 should scan all 15 channels automatically

3. DMA puts all ADC10MEM0 results into my Array[15] automatically.

All this operation should be done without any interrupts and automatic. Next SD24 trigger will come after 1ms and ADC10 should scan 15 channels again. (Scanning 15 channels takes only 50us)

I enabled the DMA interrupt to just see what is going on. I realized that interrupt occurs only one time.

What is the proper way of using ADC10 in repeated-sequence of channels - ADC10CONSEQ_3?

TI didn't provide any example code for repeated-sequence of channels mode.

void init(void)
{
	ADC10CTL0 &= ~ADC10ENC;	
	ADC10IE = 0x00;
	ADC10IFG = 0;
	ADC10CTL0 = ADC10SHT0 | ADC10ON | ADC10MSC; // ADC on, ADC10 waits for trigger from the SD24, sampling time 2us (8xADCclk), auto next conv
	ADC10CTL1 = ADC10SHP | ADC10SHS_3 | ADC10DIV_0 | ADC10SSEL_3 | ADC10CONSEQ_3; // /* Triggered by the SD24, SMCLK = 4MHz, Repeated - Sequence of channels

	ADC10CTL2 = ADC10RES | ADC10DF;
	ADC10MCTL0 = ADC10SREF_1 | ADC10INCH_15;

	// dma settings for 10 bit ADC
	DMACTL0 = DMA1TSEL__ADC10IFG0;
	__data16_write_addr((u16)&DMA1SA, (u32)&ADC10MEM0);
	__data16_write_addr((u16)&DMA1DA, (u32)&ADC.V_10bitADC[15]);
	DMA1SZ = 16; // Channels 15 to 0
	DMA1CTL = DMADT_4 | DMADSTINCR_2 | DMAEN | DMAIE; // Enable, destination address decremented, repeating single transfer

	ADC10CTL0 |= ADC10ENC; // Start ADC and wait for a trigger from the SD24
}

__interrupt void DMA_ISR(void)
{
	switch (__even_in_range(DMAIV, 16))
	{
		case DMAIV_NONE:
		{

			break;
		}

		case DMAIV_DMA0IFG:		// DMA0IFG = DMA Channel 0
		{
			break;
		}

		case DMAIV_DMA1IFG:		// DMA1IFG = DMA Channel 1
		{
			process_data();
			break;
		}

		case DMAIV_DMA2IFG:		// DMA2IFG = DMA Channel 2
		{
			break;
		}

		default:		
		{
			break;
		}
	}
}

Thanks.

over 7 years ago

0 Bruce McKenney over 7 years ago

Guru 96125 points

[I haven't used the SD24 trigger, but I expect it's the same as a timer trigger.]

There are two things going on here:
1) After the first burst (16 transfers) is done, the DMA will stop. You need to re-arm it (DMAEN=1), presumably in the ISR.
2) [Refer to SLAU208P Figure 27-9] With CONSEQ=3 and MSC=1, once the ADC10 gets a trigger it will convert continually, not waiting for another trigger. As currently coded, this ends up being harmless, since the DMA has stopped, but it isn't really what you want (particularly after you fix (1)).

I suggest you use CONSEQ=1 instead. [Refer to SLAU208P Figure 27-7] To get a burst for each trigger, you need MSC=1, but you'll need to toggle ENC (low then high) for each burst to re-arm the ADC. A good moment to do this is in the DMA ISR, at the same time as you re-arm the DMA.

0 Mehmet Fide over 7 years ago in reply to Bruce McKenney

Prodigy 80 points

Hi,

After further study of what "repeated-sequence of channels mode" is, I have realized that it is actually not what I want at all.
I concluded that getting all SD24 and ADC10 channel data synchronously without CPU overhead is not possible.
I have to re-setup some registers inside DMA interrupt.

So I configured ADC10 for "sequence of channels (autoscan)" mode instead of repeated one, ADC10CONSEQx = 01 like you suggest.
And then changed DMA to work in "single transfer" mode.

Every DMA interrupts, I re-configure ADC10 and DMA. That way works as expected.

I have one concern here. User manual says that
when any other trigger source is used (like my case), ADC10ENC must be toggled between each sequence.

But they didn't mention how long I should keep it at low while toggling.

ADC10CTL0 &= ~ADC10ENC;
// do I need some delay here? It seems yes.
ADC10CTL0 |= ADC10ENC;

Thanks.

0 Bruce McKenney over 7 years ago in reply to Mehmet Fide

Guru 96125 points

My experience: No. I've always done it back to back with no delay.

0 Mehmet Fide over 7 years ago in reply to Bruce McKenney

Prodigy 80 points

In that thread;

https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/626461?tisearch=e2e-sitesearch&keymatch=Repeated%20-%20Sequence%20of%20channels

They said that you should wait at least 3 ADC clocks. This is for ADC14 and not for ADC10. But I'm suspicious about that they use same design.

For my case, MCU clock MCLK = 8 Mhz while ADC10 clock is only 1 Mhz.

0 Bruce McKenney over 7 years ago in reply to Mehmet Fide

Guru 96125 points

The MSP432 TRM [SLAU356H sec 22.2.8.2] ADC14 section specifically mentions this requirement.

The MSP430 F5/F6 UG [SLAU208O sec 27.2.7.2] doesn't mention such a requirement. The ADC12 section [SLAU208O sec 28.2.7.2] also doesn't. I suppose it might have to do with the different bus structure.

My first guess at a symptom would be that the ENC toggling wouldn't be recognized at all, and the ADC would stall. I haven't seen this symptom in maybe 10 years of working with the ADC10.

Beyond that, I have to defer to the Wizards here.

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MSP430F6736A: SD24, ADC10 and DMA - Repeated - Sequence of channels