MSP432P401R: MSP432 PWM setting Output PIN problem

/* Port mapper configuration register */

const uint8_t port_mapping[] =
{
    //Port P3:
    PM_TA0CCR1A, PM_TA0CCR2A, PM_TA0CCR3A, PM_NONE, PM_NONE, PM_NONE, PM_NONE, PM_NONE
   //PM_TA0CCR1A, PM_TA0CCR2A, PM_TA0CCR3A, PM_NONE, PM_TA1CCR1A, PM_NONE, PM_NONE, PM_NONE

};



/* GPIO Setup for Pins 3.0-3.2 */

MAP_PMAP_configurePorts((const uint8_t *) port_mapping, PMAP_P3MAP, 1,
                          PMAP_DISABLE_RECONFIGURATION);

MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P3,
                                                GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2, GPIO_PRIMARY_MODULE_FUNCTION);



 /* Configure TimerA0 without Driverlib (CMSIS style register access) */
TIMER_A0->CCR[0] = PWM_PERIOD;
TIMER_A0->CCTL[1] = TIMER_A_CCTLN_OUTMOD_7;                      // CCR1 reset/set
TIMER_A0->CCTL[2] = TIMER_A_CCTLN_OUTMOD_7;                      // CCR2 reset/set
TIMER_A0->CCTL[3] = TIMER_A_CCTLN_OUTMOD_7;                      // CCR3 reset/set
TIMER_A0->CTL = TIMER_A_CTL_SSEL__SMCLK | TIMER_A_CTL_MC__UP | TIMER_A_CTL_CLR;  // SMCLK, up mode, clear TAR


//set duty cycle
TIMER_A0->CCR[1] = (PWM_PERIOD * 200/255);              // CCR1 PWM duty cycle
TIMER_A0->CCR[2] = (PWM_PERIOD * 200)/255;                // CCR2 PWM duty cycle
TIMER_A0->CCR[3] = (PWM_PERIOD * 0)/255;                // CCR3 PWM duty cycle