MSP430F5529: PWM + Phase shift

#include <msp430.h> 


/**
 * main.c
 */

void main(void)
{

    WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  /*P1DIR |= BIT0;                            // ACLK set out to pins
  P1SEL |= BIT0;
  P2DIR |= BIT2;                            // SMCLK set out to pins
  P2SEL |= BIT2;
  P7DIR |= BIT7;                            // MCLK set out to pins
  P7SEL |= BIT7;*/

  P5SEL |= BIT2+BIT3;                       // Port select XT2
  P5SEL |= BIT4+BIT5;                       // Port select XT1

  UCSCTL6 &= ~XT2OFF;                       // Set XT2 On
  UCSCTL6 &= ~XT1OFF;                       // Set XT1 On
  UCSCTL6 |= XCAP_3;                        // Internal load cap

  UCSCTL1 = DCORSEL_5;
  UCSCTL2 = FLLD_1 + (218);

  // XT1 is by default on as it is used default reference for the FLL - internal load caps?
  // Loop until XT1,XT2 & DCO stabilizes
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  UCSCTL6 &= ~XT2DRIVE0;                    // Decrease XT2 Drive according to
                                            // expected frequency
  UCSCTL4 |= SELA_0 + SELS_5;               // Select SMCLK, ACLK source and DCO source

        P5SEL |= 0x80;
        P5DIR |= 0x80;
      //  P5OUT |= BIT7;
        P7SEL |= 0x50;
        P7DIR |= 0xFF;
        //P7OUT |= 0x50;
        P3SEL |= 0x60;
        P3DIR |= 0xFF;
        //P3OUT &= ~(BIT4+BIT5);



        TB0CCR0 = 89;

        //TB0CCTL1 |= BIT2;
      // TB0CCTL2 |= BIT2;
      // TB0CCTL4 |= BIT2;
        TB0CCTL1 = OUTMOD_7;
        TB0CCR1 = 68;

        TB0CCTL2 = OUTMOD_4 + CCIE;
        TB0CCR2 = 18;

        TB0CCTL4 = OUTMOD_4 + CCIE;
        TB0CCR4 = 14;

        TB0CCTL5 = OUTMOD_4 + CCIE;
        TB0CCR5 = 32;

        TB0CCTL6 = OUTMOD_4 + CCIE;
        TB0CCR6 = 50;

        TB0CTL = TBSSEL_2 + MC_1 + TBCLR + TAIE;

        __bis_SR_register(LPM0_bits + GIE);






while (1);




}


#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=TIMERB0_VECTOR
__interrupt void TIMERB0_ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMERB0_VECTOR))) TIMERB0_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch( __even_in_range(TB0IV,12) )
    {
    case 4:
        if (TB0CCR2 == 18)
        {
            TB0CCR2 = 86;
        }
        else
        {
            TB0CCR2 = 18;
        }
        break;
    case 8:
           if (TB0CCR4 == 14)
           {
               TB0CCR4 = 36;
           }
           else
           {
               TB0CCR4 = 14;
           }
           break;
    case 10:
           if (TB0CCR5 == 32)
           {
               TB0CCR5 = 54;
           }
           else
           {
               TB0CCR5 = 32;
           }
           break;
    case 12:
           if (TB0CCR6 == 50)
           {
               TB0CCR6 = 72;
           }
           else
           {
               TB0CCR6 = 50;
           }
           break;
    default:
        break;
    }

}



//the interrupts doesn't seem to work. Can you tell me where am I going wrong?