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MSP430F5310: Baud rate change from 4800 to 19200 - seeing high amount of errors

Ian Cannon
Prodigy 50 points
Part Number: MSP430F5310

 I am changing the Modbus baud rate on my MSP430f5310 part from 4800 to 19200 and am seeing some higher than expected TX errors - about 9.5% when the max TX Error from timer setup is expected to be 4.6%, shown in Table 36-5 below. 

Could this be a limitation of the part? What can I do to overcome this high error rate? Are there measurements I can take to more accurately diagnose my issue?

Auxillary information: I was successfully able to set up the part with 4800 baud without any send or receive errors. I am working in a relatively noise-free environment. I am compiling C code using Code Composer Studio. The highlighted areas represent the changes I made to increase the baud rate.

Please Advise.

  • 0
    TI__Guru 56685 points

    Hello Ian,

    From the table above, total error of a setting is going to be the addition of the absolute value of both the negative and positive side. So total possible error for your settings on Tx side is closer to 7.8% and 9.7% on the Rx side. This is assuming no error introduced from your clock source as well (unlikely).  

    If you still want to use the same BRCLK and baud rate combination, but want to lower error, then I would turn the oversampling off and adjust the over settings to what is in Table 36-4 as shown below. Alternatively, you can adjust BRCLK Frequency to a higher value to reduce error as well.

  • 0 in reply to Jace H
    Prodigy 50 points

    Thanks for your response. I would like to avoid changing the BRCLK frequency as there are other communication protocols that are dependant on it. Therefore I tried turning oversampling off and changed the other values according to the table.

    I am still seeing a 6.7% error rate on messages, taken from a sample of 130,000 messages. Is there anything else I can do to reduce the error rate?

    Here is a snippet of the setup:

    UCA0BRW = 54;
UCA0MCTL = UCBRS_5 + UCBRF_0;


  • 0 in reply to Ian Cannon
    TI__Guru 56685 points
    Ian,

    What clock source are you using for the USCI Module? This is the most likely source of the extra error.
  • 0 in reply to Jace H
    Prodigy 50 points

    I am using TA0, setup below:

    	//Program Timer 0 capture 0 to capture on rising and falling edges
    //       SMCLK     /8       up to 0xffff  Timer clear   TAIFG interrupt DISABLE
    TA0CTL = 0x200     | 0xc0   | 0x20        | 0x4         | 0x0;                   //0x0E24

    //         Cap rising+falling + Input A    Sync+ Cap     Interrupt Enabled
    TA0CCTL0 = 0xc000                          | 0x900       | 0x10;

  • 0 in reply to Ian Cannon
    Prodigy 50 points
    It looks like UCB1 is an open clock (would not affect other operations on the chip). Would that be capable of prividing a higher clock rate?
  • 0 in reply to Ian Cannon
    TI__Guru 56685 points

    Ian,

    I am confused on how you are using a timer to clock the USCI module. The only clocks available to be used for th eUSCI module are ACLK, SMALCK, or an external clock fed into the USCI module using a UCAxCLK pin. you choice should be reflected within the UCAxCTL1 Register and the UCSSELx bits. Which clock are you feeding into the USCI? ALCK/SMCLK/External? and what source is driving that clock?

  • 0 in reply to Jace H
    Prodigy 50 points

    Sorry, I was looking in the wrong place. It is based on SMCLK

     P3SEL |= BIT3 | BIT4;                     // P3.3,4 = USCI_A0 TXD/RXD
 UCA0CTL1 |= UCSWRST;                      // A0 CTRL register is reset **Put UART state machine in reset**
 UCA0CTL1 |= UCSSEL__SMCLK;                // A0 SMCLK (clock source 2)

  • 0 in reply to Ian Cannon
    TI__Guru 56685 points
    Ian,

    What is the source of SMCLK? If its DCO, then you could have extra error thrown in via the DCO. You could use a precision external xtal to eliminate this error, but it might be better served to change baud rate settings to achieve lower error.

    Also, another thought is if you are using deep LPMs (say LPM3) between transactions, your error rate will go up due to the possible missing of the first byte if your baud rate is too high.

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