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CCS/MSP430F5529: MSP430F5529 16 MHz External Crystal UART Configuration

Gabriel Denham
Prodigy 60 points
Part Number: MSP430F5529
Other Parts Discussed in Thread: MSP430WARE

Tool/software: Code Composer Studio

Hi,

I am trying to configure my MSP430F5529 MCU with an external crystal oscillator on port pins P5.2 and P5.3 (XT2IN and XT2OUT).  The external crystal oscillator is a 16MHz XTAL.I looked through the MSP430F5529 user's guide and datasheet, and I've added some of my UART code below.  I also have SMCLK source selected and a divider of 2.  Do I need to add any additional control register fields to achieve my initialization?

P3SEL |= BIT3 + BIT4;                                      // P3.3 and P3.4 ->  UART Ports

P5SEL |= BIT2 + BIT3;                                      // P5.2 -> XT2IN and P5.3 -> XT2OUT

UCSCTL6 &= ~XT2OFF;                                   // Set XT2 On

UCSCTL4 = SELS_5;                                        // SELS_5 -> XT2CLK (Selects SMCLK)

UCSCTL5 = DIVS_1;                                        // DIVS_1 -> SMCLK source divider (divide by 2)



UCSCTL6 = XT2BYPASS | XT2DRIVE_1;       //** Test Conditions for Crystal Oscillator XT2 **

                                                                          // in the frequency range of 8 to 16 MHz

                                                                         // XT2BYPASS -> XT2 sourced from external crystal

                                                                         // Increased drive strength XT2 oscillator



UCA0CTL1 |= UCSWRST;                             // **Put state machine in reset**

UCA0CTL1 |= UCSSEL_2;                            // Clock Source SMCLK UCA0BR0 = 69; // 8MHz 115200

UCA0BR1 = 0;                                               // 8MHz 115200

UCA0MCTL = UCBRS_4 + UCBRF_0;         // Modulation UCBRSx = 4

UCA0CTL1 &= ~UCSWRST;                         // **Initialize USCI state machine**

UCA0IE |= UCRXIE;                                      // Enable USCI_A0 RX interrupt

Thanks

  • 0
    Guru 301610 points

    You need to wait until the crystal has started up, and then clear the fault flag to disable the fail-safe fallback (see section 5.2.12 of the User's Guide).

    The example program MSP430F55xx_UCS_08.c shows how to do this:

      ...
  P5SEL |= BIT2+BIT3;                       // Port select XT2

  UCSCTL6 &= ~XT2OFF;                       // Enable XT2
  UCSCTL3 |= SELREF_2;                      // FLLref = REFO
                                            // Since LFXT1 is not used,
                                            // sourcing FLL with LFXT1 can cause
                                            // XT1OFFG flag to set
  UCSCTL4 |= SELA_2;                        // ACLK=REFO,SMCLK=DCO,MCLK=DCO

  // Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  UCSCTL6 &= ~XT2DRIVE0;                    // Decrease XT2 Drive according to
                                            // expected frequency
  UCSCTL4 |= SELS_5 + SELM_5;               // SMCLK=MCLK=XT2
  ...
  • 0
    TI__Genius 10860 points
    Hi Gabriel,

    I can only second Clemens' advise, it should solve your problem.
    In general the code examples provided in MSP430Ware are a good starting point with the different on chip modules as they showcase different possible configurations.

    Best regards,
    Britta
  • 0
    Guru 34453 points

    For BR setup can be used calculator...6038.MSP430UartCalc.rar

  • 0
    TI__Genius 10860 points
    Hi,

    as I didn't hear back from you in a while I assume that your issue has been solved.
    Please go ahead and verify the given answer to also help other users that might run into the same issue.

    Note that I'll go ahead and close this thread. Replying to the thread will re-open it if necessary at some point.

    Best regards,
    Britta

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