CCS/MSP430G2553: MSP430G2553 Timer speed

Tool/software: Code Composer Studio

With the following code, I would await, that the pulse at P2.1 is 27µs, if I load 27 in the variable "pulswidth".

However: to get a 27µs - Pulswidth, I need to load 41. That is strange, because on page 357 in the documentation (SLAU144J) one can read:

"The 16-bit timer/counter register TAR, increments or decrements with each rising edge of the clock signal....."

So is it a bug or maybe I do someting wrong?

Franz Peter Zantis

    BCSCTL1 |= CALBC1_1MHZ;            //DCOCLK = 1MHz
    BCSCTL2 = 0;                    //MCLK = SMCLK = DCOCLK
    DCOCTL  |= CALDCO_1MHZ;            //frequency: 1MHz internal
    WDTCTL = WDTPW + WDTHOLD;       //Stop WatchDogTimer

    P2SEL |= BIT1;            //P2.1 für Timer output
    P2DIR |= BIT1;            //P2.1 für Timer output
    P2SEL2 &= ~BIT1;        //P2.1 für Timer output
    TA1CTL |= MC_0;            //stop the timer
    TA1CTL |= TASSEL_2;        //use SMCLK as timer-clock
    TA1CTL |= ID_0;            //clock divider=1
    TA1CCTL1 = OUTMOD_7;    //reset/set depending on register CCR1
    TA1CCR0 = 0xFFFE;        //longest period in up mode; this can be changed by the Poti or via SPI
    TA1CCR1 = pulswidth;    //Pulswidth
    TA1CTL |= MC_1;            //start Timer in up-mode; runs until TA1CCR0 is reached and decreases again to 0