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MSP432P4111: ADC14 Multichannel Sequence DMA ping-pong limitations

Part Number: MSP432P4111

My current setup is: 

  • MSP432P4111 custom board
  • SimpleLink MSP432P4SDK 2.10.0.14
  • CCS V7.3.0
  • XDCTools 3.50.5.12
  • Compiler TI v17.9.0.STS

Ideally I would like to capture ADC Channels A3, A2, A1, A0 sequentially and repeatedly via DMA ping-pong mode. 
My ideal scenario would be capturing 2048 samples (1024 ping, 1024 pong), running at the 1 Megasample rate.  

The best I have been able to do is the source code below.  Where i'm capturing 32 samples via DMA ping-pong mode (32 ping, 32 pong).  Using the source increment feature so the DMA steps through ADC_MEM0 to ADC_MEM31.  I don't see a way of doing a repeated sequence DMA Ping Pong mode so the DMA will automatically loop around and repeatedly capture A3, A2, A1, A0, A3, A2, A1, A0, A3, A2... My current method of 32 sample DMA's is still to slow to sustain the 1Msample rate. 

I've searched through the forums, and haven't had any luck finding a possible solution.  Only bits and pieces of incomplete answers.  That brings up 3 questions:

  1. Is there an example of a multi-channel sequence repeat mode ADC example with a large ping-pong DMA buffer?
  2. Any suggestions of how to better implement this type of DMA, that I'm missing?
  3. My example only works if I call the   ADC14_toggleConversionTrigger(); in the setup and DMA ISR.  This is having a timing impact on my current system.  What am I doing incorrectly to require this call?

#define DMA_ADC_CHAN       7
#define DMA_CAPTURE_SIZE   32
#define ADC_HS_BLOCK_SIZE  256
#define ADC_HS_BUFF_SIZE   (2*ADC_HS_BLOCK_SIZE)

#pragma DATA_ALIGN(dmaCtrlTable, 256)
uint8 dmaCtrlTable[256];

#pragma DATA_ALIGN(adcDmaBuf, 256)
uint32 adcDmaBuf[DMA_CAPTURE_SIZE*2];

#pragma DATA_ALIGN(adcHsSamples, 256)
uint32 adcHsSamples[ADC_HS_BUFF_SIZE];

int16  adcHsSampleIdx = 0;
int16  skipBlock = 0;

void ADCStartDmaCaptureSequence(void)
{
   int16 idx = 0, inputSelect;
   uint32 adcMem = 0;

   ADC14_configureMultiSequenceMode(ADC_MEM0, ADC_MEM31, false);
   // capture A3, A2, A1, A0, from ADC_MEM0 to ADC_MEM31 (32 samples)
   for( idx = 0; idx < DMA_CAPTURE_SIZE; idx ++ )
   {
      inputSelect = idx & 0x00000003;
      switch(inputSelect)
      {
      case 0:
         ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                  ADC_INPUT_A3, false);
         break;
      case 1:
         ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                  ADC_INPUT_A2, false);
         break;
      case 2:
         ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                  ADC_INPUT_A1, false);
         break;
      case 3:
         ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                  ADC_INPUT_A0, false);
         break;
      }
   }

   ADC14_setSampleHoldTime(ADC_PULSE_WIDTH_4, ADC_PULSE_WIDTH_4);
   ADC14_setSampleHoldTrigger(ADC_TRIGGER_ADCSC, false);

   // Now configure DMA
   DMA_enableModule();
   DMA_setControlBase(dmaCtrlTable);
  /*
   * Primary DMA Channel, ADC14
   * Size = 32bits
   * Source Increment = 32bits
   * Destination Increment = 32bits
   * Arbitration = 32 , no other sources
   */
   DMA_setChannelControl(UDMA_PRI_SELECT | DMA_CH7_ADC14,
       UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_32);
   DMA_setChannelTransfer(UDMA_PRI_SELECT | DMA_CH7_ADC14,
       UDMA_MODE_PINGPONG, (void*) &ADC14->MEM[0],
       &adcDmaBuf[0], DMA_CAPTURE_SIZE);

   DMA_setChannelControl(UDMA_ALT_SELECT | DMA_CH7_ADC14,
       UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_32);
   DMA_setChannelTransfer(UDMA_ALT_SELECT | DMA_CH7_ADC14,
       UDMA_MODE_PINGPONG, (void*) &ADC14->MEM[0],
       &adcDmaBuf[DMA_CAPTURE_SIZE], DMA_CAPTURE_SIZE);

   adcHsSampleIdx = 0;
   DMA_assignInterrupt(DMA_INT1, DMA_ADC_CHAN);
   Interrupt_enableInterrupt(INT_DMA_INT1);
   DMA_assignChannel(DMA_CH7_ADC14);
   DMA_clearInterruptFlag(0x07);
   DMA_enableChannel(DMA_ADC_CHAN);

   //Interrupt_enableInterrupt(INT_ADC14);
   ADC14_enableSampleTimer(ADC_AUTOMATIC_ITERATION);
   ADC14_enableConversion();
   //ADC14_enableInterrupt(ADC_INT31); // Interrupt after ADC_MEM3 complete
   ADC14_toggleConversionTrigger();
   SetStatus1Low();
}

//__attribute__((ramfunc))
void Dma1ISR(UArg arg0)
{
   BOOL dmaEvent = FALSE;
   uint32 select = DMA_getChannelAttribute(7);
   SetStatus1High();

   ADC14_toggleConversionTrigger();  // does not work without this!
   if ( select & UDMA_ATTR_ALTSELECT )
   {
      DMA_setChannelControl(UDMA_PRI_SELECT | DMA_CH7_ADC14,
          UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_32);
      DMA_setChannelTransfer(UDMA_PRI_SELECT | DMA_CH7_ADC14,
          UDMA_MODE_PINGPONG, (void*) &ADC14->MEM[0],
          &adcDmaBuf[0], DMA_CAPTURE_SIZE);
      memcpy( &adcHsSamples[adcHsSampleIdx], &adcDmaBuf[0], DMA_CAPTURE_SIZE * sizeof(uint32));
      if( (adcHsSampleIdx + DMA_CAPTURE_SIZE) <  ADC_HS_BUFF_SIZE )
         adcHsSampleIdx += DMA_CAPTURE_SIZE;
      else
         adcHsSampleIdx = 0;
   }
   else
   {
      DMA_setChannelControl(UDMA_ALT_SELECT | DMA_CH7_ADC14,
          UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_32);
      DMA_setChannelTransfer(UDMA_ALT_SELECT | DMA_CH7_ADC14,
          UDMA_MODE_PINGPONG, (void*) &ADC14->MEM[0],
          &adcDmaBuf[DMA_CAPTURE_SIZE], DMA_CAPTURE_SIZE);
      memcpy( &adcHsSamples[adcHsSampleIdx], &adcDmaBuf[DMA_CAPTURE_SIZE], DMA_CAPTURE_SIZE * sizeof(uint32));
      if( (adcHsSampleIdx + DMA_CAPTURE_SIZE) <  ADC_HS_BUFF_SIZE )
         adcHsSampleIdx += DMA_CAPTURE_SIZE;
      else
         adcHsSampleIdx = 0;
   }

   if(adcHsSampleIdx == ADC_HS_BLOCK_SIZE )
      dmaEvent = TRUE; // insert event post here
   else if( adcHsSampleIdx == 0 )
      dmaEvent = TRUE; // insert event post here

   SetStatus1Low();
}

  • Maybe this example might provide some ideas.  It does not ping and pong like what you are asking but it could be coded to more specifically emulate that function.  The DMA is operating in scatter-gather mode and collecting the 32 samples from the ADC much like you are doing.  Every 1K samples a port interrupt is fired to alert the CPU that the 1K is ready, while the next 1K is being measured.  A way to make it continuous is to have the last scatter-gather task point back to the beginning of the task list.  

    ADC14_configureMultiSequenceMode(ADC_MEM0, ADC_MEM31, false);

    You have set the repeatMode to false.  This means that you will get a single sequence of channels instead of a repeated sequence of channels and will need to retrigger to get the sequence to restart.  I thought that you also had to disable and then re-enable the enable convert as well.

    Regards,

    Chris

  • Chris,

    Thanks for that info.  I seem to be off to a good start, i just ran into a hiccup with this approach.

    First here's what i'm trying to do:

    1. Configure ADC for multichannel repeated sequence mode
    2. Create 68 DMA scatter gather tasks ( I have attached dmaTasks.c and dmaTasks.h which define the tasks similar to the example you provided)
    1. 32 peripheral ADC DMAs (32 transfer of 32 conversions MEM0->MEM31)
    2. 1 8 bit mem scatter gather task to set the Port 5 IFG Pin 0 flag
    3. 1 32 bit mem scatter gather task to do a SW interrupt for P5 ( NVIC->STIR = 55)
    4. 32 Peripheral ADC DMAs( 32 transfers of 32 conversions MEM0->MEM1
    5. 1 8 bit mem scatter gather task to set the Port 5 IFG Pin 0 flag
    6. 1 32 bit mem scatter gather task to do a SW interrupt for P5 ( NVIC->STIR = 55)
    • Enable Conversions
    • Enable DMA channel 7
    • Kickstart ADC DMA by doing a  ADC14_toggleConversionTrigger();

    When I initialize the transfers using the code below

    void ADCStartDmaCaptureSequence(void)
    {
       int16 idx = 0, inputSelect;
       uint32 adcMem = 0;
    
       #define DMA_CAPTURE_SIZE   32
       adcSampCfg.mode = ADC14_MODE_TGC;
       ADC14_configureMultiSequenceMode(ADC_MEM0, ADC_MEM31, true);
       // capture A3, A2, A1, A0, from ADC_MEM0 to ADC_MEM31 (32 samples)
       for( idx = 0; idx < DMA_CAPTURE_SIZE; idx ++ )
       {
          inputSelect = idx & 0x00000003;
          switch(inputSelect)
          {
          case 0:
             ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                      ADC_INPUT_A3, false);
             break;
          case 1:
             ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                      ADC_INPUT_A2, false);
             break;
          case 2:
             ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                      ADC_INPUT_A1, false);
             break;
          case 3:
             ADC14_configureConversionMemory(1 << idx, ADC_VREFPOS_AVCC_VREFNEG_VSS,
                      ADC_INPUT_A0, false);
             break;
          }
       }
    
       ADC14_setSampleHoldTime(ADC_PULSE_WIDTH_4, ADC_PULSE_WIDTH_4);
       ADC14_setSampleHoldTrigger(ADC_TRIGGER_ADCSC, false);
    
       DMA_enableModule();
       DMA_setControlBase(dmaCtrlTable);
       /*
        * Setup the DMA + ADC14 interface
        *  Disabling channel attributes
        */
       DMA_disableChannelAttribute(DMA_CH7_ADC14,
                                        UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
                                        UDMA_ATTR_HIGH_PRIORITY |
                                        UDMA_ATTR_REQMASK);
       DMA_enableChannelAttribute(DMA_CH7_ADC14, UDMA_ATTR_USEBURST);
       /*
        * Set the DMAs primary channel for peripheral scatter gather mode
        */
       DMA_setChannelScatterGather(DMA_CH7_ADC14, NUMBER_OF_TASKS, (void*)&adcDmaTaskList[0], false);
       DMA_assignChannel(DMA_CH7_ADC14);
       GpioEnableAdcPort5Interrupts();
       ADC14_enableSampleTimer(ADC_AUTOMATIC_ITERATION);
       ADC14_enableConversion();
       ADC14_toggleConversionTrigger();
       DMA_enableChannel(7);
    }

    MY DMA works right up until the Item 2.d. above. 

    • The DMA makes it through the first 32 ADC DMA tasks. 
    • The DMA Controller sets the P5->IFG = 0x01
    • The DMA Controller generates a SWINT (NVIC-STIR = 55)
    • The PORT 5 Interrupt Occurs for IFG = 0x01, but I get no further DMA Transfers.  
    • No Further DMA tasks appear to run.  

    There is a clue in my DMA Control Table Which I captured after setting a breakpoint in my port5 interrupt. The Memory browser screen shot is marked up below

    1. You see in the the Pimary channel 7 section we have pending DMA tasks (it looks like 34 tasks if you assume the value is in bytes...0x87 = 136 / 4 words per task entry = 34 tasks)
    2. You see in the Primary channel 5 section we have completed the NVIC write. 
    3. The problem is, my DMA appear to be halted...ie no more tasks are running.  

    /*******************************************************************************
     Auto Generated File: createDmaTaskList.py
    *******************************************************************************/
    /*******************************************************************************
     Includes
    *******************************************************************************/
    #include "dmaTasks.h"
    #include <ti/devices/msp432p4xx/driverlib/driverlib.h>
    
    /*******************************************************************************
     Variable Declarations
    *******************************************************************************/
    const uint32 swTrigP5Int  = 55;
    const uint8  forcePortISR0 = 0x01;
    const uint8  forcePortISR1 = 0x02;
    
    /*******************************************************************************
     DMA Task List
    *******************************************************************************/
    const DMA_ControlTable adcDmaTaskList[NUMBER_OF_TASKS] =
    {
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   0 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   1 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   2 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   3 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   4 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   5 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   6 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   7 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   8 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[   9 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  10 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  11 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  12 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  13 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  14 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  15 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  16 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  17 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  18 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  19 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  20 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  21 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  22 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  23 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  24 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  25 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  26 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  27 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  28 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  29 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  30 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  31 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
        /**************************************************************
           Generate Port Interrupt for ping/pong style interrupt
        **************************************************************/
        DMA_TaskStructEntry(1, UDMA_SIZE_8,
           UDMA_SRC_INC_8, (void *)&forcePortISR0,
           UDMA_DST_INC_8, (void *)&P5->IFG,
           UDMA_ARB_1, (UDMA_MODE_MEM_SCATTER_GATHER)
           ),
        DMA_TaskStructEntry(1, UDMA_SIZE_32,
           UDMA_SRC_INC_32, (void *)&swTrigP5Int,
           UDMA_DST_INC_32, (void *)&NVIC->STIR,
           UDMA_ARB_1, (UDMA_MODE_MEM_SCATTER_GATHER)
        ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  32 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  33 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  34 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  35 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  36 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  37 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  38 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  39 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  40 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  41 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  42 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  43 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  44 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  45 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  46 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  47 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  48 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  49 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  50 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  51 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  52 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  53 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  54 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  55 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  56 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  57 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  58 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  59 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  60 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  61 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  62 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  63 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_PER_SCATTER_GATHER)
       ),
        /**************************************************************
           Generate Port Interrupt for ping/pong style interrupt
        **************************************************************/
        DMA_TaskStructEntry(1, UDMA_SIZE_8,
           UDMA_SRC_INC_8, (void *)&forcePortISR1,
           UDMA_DST_INC_8, (void *)&P5->IFG,
           UDMA_ARB_1, (UDMA_MODE_MEM_SCATTER_GATHER)
           ),
        DMA_TaskStructEntry(1, UDMA_SIZE_32,
           UDMA_SRC_INC_32, (void *)&swTrigP5Int,
           UDMA_DST_INC_32, (void *)&NVIC->STIR,
           UDMA_ARB_1, (UDMA_MODE_MEM_SCATTER_GATHER)
        )
    };
    
    dmaTasks.h

  • Can you change the order of when you move from peripheral to memory scatter gather?

    The last ADC transfer before setting up the GPIO is peripheral and I think it should be memory.   Similarly the transfer to the NVIC before you start up the ADC conversions should be Peripheral.  

       DMA_TaskStructEntry(DMA_BLOCK_SIZE, UDMA_SIZE_32,
          UDMA_SRC_INC_32, &ADC14->MEM[0],
          UDMA_DST_INC_32, (void *)&adcDmaBuf0[  31 * DMA_BLOCK_SIZE],
          UDMA_ARB_32, (UDMA_MODE_MEM_SCATTER_GATHER)
       ),
        /**************************************************************
           Generate Port Interrupt for ping/pong style interrupt
        **************************************************************/
        DMA_TaskStructEntry(1, UDMA_SIZE_8,
           UDMA_SRC_INC_8, (void *)&forcePortISR0,
           UDMA_DST_INC_8, (void *)&P5->IFG,
           UDMA_ARB_1, (UDMA_MODE_MEM_SCATTER_GATHER)
           ),
        DMA_TaskStructEntry(1, UDMA_SIZE_32,
           UDMA_SRC_INC_32, (void *)&swTrigP5Int,
           UDMA_DST_INC_32, (void *)&NVIC->STIR,
           UDMA_ARB_1, (UDMA_MODE_PER_SCATTER_GATHER)
        ),

  • Wanting to see if this helped resolve the issue and if you are able to move forward.

    Chris

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