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MSP430G2553: Understanding the clock-system

Elude Mobister
Prodigy 165 points
Part Number: MSP430G2553

I was looking through the MSP430x2xx Family User doc. and was trying to take some notes about the clock-system. I think I would feel better if someone more experienced would take a look over them and confirm that I'm not actually misunderstanding/misinterpreting anything. Furthermore, if these notes might help someone else get started with MPS430 feel free to use them:

master-clock (MCLK) - used for the CPU,                  - can be sourced from: DCO, LFXT1, VLO
sub-main clock (SMCLK) - used for peripherals,      - can be sourced from: DCO, LFXT1, VLO
auxiliary clock (ACLK) - used for peripherals,          - can be sourced from: LFXT1, VLO
 
BCSCTL1      - basic clock system control 1 (responsible for the aux. clock (ACLK)) 
Use DIVA_0 .... DIVA_3 to divide the frequency by 1, 2, 4, and 8. In some MCU models the XTS bit is used for LFXT1 mode selection.
When XTS bit is reset, low-frequency mode is selected, when it is set, high-frequency mode is selected.
Note: the MSP430G2553 does now support setting this bit (XTS).
BCSCTL2     - basic clock system control 2 (responsible for the master and sub-main clock (MCLK))
Use SELM_0 & SELM_1 (to source from DCOCLK ), SELM_2 & SELM_3 (for VLOCLK or LFXTCLK) 
Use DIVM_0 .... DIVM_3 (for MCLK) to divide the frequency by 1,2,4, and 8.
Use DIVS_0 .... DIVS_3 (for SMCLK) to divide the frequency by 1,2,4, and 8.
BCSCTL3     - basic clock system control 3 (responsible for external oscillator (LFXT1)
Use LFXT1S_0 (for ext. crystal), LFXT1S_1 (reserved), LFXT1S_2 (for VLO), LFXT1S_3 (for digital input signal).
XCAP<x> to choose from 1-pF, 6-pF, 10-pF, or 12.5-pF for internal capacitors for external crystals oscillators. 
IE1       - interrupt enable register
IFG1     - interrupt flag register
So, let's consider a use-case: (say) I'd like to set my MCU for an application that uses the MCLK for its CPU and sources from the internal DCO, the SMCLK also should be sourced from the DCO. I would choose the BCSCTL2 (referencing the user-guide) 
BCSCTL2 = SELM_2 + DIVM_0 + /* skipping SELS */ DIVS_0; /* skipping DCOR*/

// SELM_2 --> selects src from DCOCLK
// DIVM_0 --> divides freq by 1 (see DIVM_x header options)
// skipping SELS because bit is set to 0 by default which means SMCKL will src from DCOCLK by default, or should I use RSEL0?
// DCOR not applicable (for the MSP430G2553) is this correct??

Now, do I need to (since DCOCLK has been referenced at least twice) also be set (prior) to the BCS+ or can I just place it after the BCSCTL2 statement?

DCOCTL = CAL_DCO_1MHZ;

This two lines should set the clock-system to what I need, correct?

  • 0
    TI__Genius 10860 points

    Hi Elude,

    I think it will probably help others to go through what you've extracted from the Family User's Guide.

    Thanks for sharing!

    Yes, the two lines you've posted should do what you want. Before calibrating the DCO you might want to check though if the calibration constant had been erased before, as setting it again could trap the CPU.

    You can check the code examples we provide to get started. Have a look at the TI Resource Explorer and browse for the MSP430G2553.

    Best regards,

    Britta

  • 0 in reply to Britta Ruelander
    Prodigy 165 points
    Thank you for taking a look and for the links.

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