MSP430FR6989: How to write FRAM program

Hello,

You can try below example code. If set MPUSEG2WE, then no violation will occur, if not, there will be write violation causing NMI interrupt.

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//******************************************************************************
//  MSP430FR69xx Demo - MPU Write protection violation - Interrupt notification
//
//  Description: The MPU segment boundaries are defined by:
//  Border 1 = 0x6000 [MPUSEGB1 = 0x0600]
//  Border 2 = 0x8000 [MPUSEGB2 = 0x0800]
//  Segment 1 = 0x4400 - 0x5FFF
//  Segment 2 = 0x6000 - 0x7FFF
//  Segment 3 = 0x8000 - 0x23FFF
//  Segment 2 is write protected. Any write to an address in the segment 2 range
//  causes an NMI interrupt. The LED toggles after accessing SYS NMI ISR.
//
//  ACLK = n/a, MCLK = SMCLK = default DCO
//
//
//           MSP430FR6989
//         ---------------
//     /|\|               |
//      | |               |
//      --|RST            |
//        |               |
//        |           P1.0|-->LED
//
//   William Goh
//   Texas Instruments Inc.
//   April 2014
//   Built with IAR Embedded Workbench V5.60 & Code Composer Studio V6.0
//******************************************************************************
#include <msp430.h>

unsigned char SYSNMIflag = 0;
unsigned int *ptr = 0;
unsigned int Data = 0;

#pragma LOCATION (Udata, 0x6004)
unsigned int Udata = 0;

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

  // Configure GPIO
  P1DIR |= BIT0;                            // Configure P1.0 for LED

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // Configure MPU
  MPUCTL0 = MPUPW;                          // Write PWD to access MPU registers
  MPUSEGB1 = 0x0600;                        // B1 = 0x6000; B2 = 0x8000
  MPUSEGB2 = 0x0800;                        // Borders are assigned to segments
  
  //  Segment 1 - Execute, Read
  //  Segment 2 - Execute, Read
  //  Segment 3 - Execute, Read
  MPUSAM = MPUSEG1RE | MPUSEG1XE |
           MPUSEG2RE | MPUSEG2XE |MPUSEG2WE|
           MPUSEG3RE | MPUSEG3XE |
           MPUSEGIRE | MPUSEGIWE| MPUSEGIXE;
  MPUCTL0 = MPUPW | MPUENA | MPUSEGIE;    // Enable MPU protection
                                          // MPU registers locked until BOR
  Data = 0x88;

  // Cause an MPU violation by writing to segment 2+
  ptr = (unsigned int *)0x6002;
  *ptr = Data;

  Udata = 0x55;

  __delay_cycles(100);

  while(SYSNMIflag)                         // Has violation occurred due to Seg2
  {
    P1OUT ^= BIT0;                          // Toggle LED
    __delay_cycles(100000);                 // Delay to see toggle
  }

  // No violation - trap here
  while(1);
}

// System NMI vector
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = SYSNMI_VECTOR
__interrupt void SYSNMI_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(SYSNMI_VECTOR))) SYSNMI_ISR (void)
#else
#error Compiler not supported!
#endif

{
  switch (__even_in_range(SYSSNIV, SYSSNIV_CBDIFG))
  {
  case SYSSNIV_NONE: break;
  case SYSSNIV_RES02: break;
  case SYSSNIV_UBDIFG: break;
  case SYSSNIV_RES06: break;
  case SYSSNIV_MPUSEGPIFG: break;
  case SYSSNIV_MPUSEGIIFG: break;
  case SYSSNIV_MPUSEG1IFG: break;
  case SYSSNIV_MPUSEG2IFG:
    MPUCTL1 &= ~MPUSEG2IFG;                 // Clear violation interrupt flag
    SYSNMIflag = 1;                         // Set flag
    break;
  case SYSSNIV_MPUSEG3IFG: break;
  case SYSSNIV_VMAIFG: break;
  case SYSSNIV_JMBINIFG: break;
  case SYSSNIV_JMBOUTIFG: break;
  case SYSSNIV_CBDIFG: break;
  default: break;
  }
}

B.R

Winter