Compiler/MSP430I2020: IAR

//------------------------------
// Main loop: 
//------------------------------	
	
		while(uc_wait_sleep_cnt==0)
		{
			//LPM3;					
			chg_uartrx_to_io_pin();
			uc_action |=F_Action_Sleep;
			LPM4;		
			asm("nop");			
			uc_action &= ~F_Action_Sleep;
			uc_wait_sleep_cnt = C_Wait_Slp_Time;	// go into the main loop 
		}
		
		
		
		
		
//------------------------------
// UART 
//------------------------------


void uart_init(void) {
    // Configuration for 115200 UART with SMCLK at 16384000
    // These values were generated using the online tool available at:
    // http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html
    EUSCI_A_UART_initParam uartConfig = {
        EUSCI_A_UART_CLOCKSOURCE_SMCLK,          // SMCLK Clock Source
        19,	                         			 // BRDIV  //25,       
        14,                                      // UCxBRF = 14
        34,                                      // UCxBRS = 34
        EUSCI_A_UART_EVEN_PARITY,                // 1 even Parity
        EUSCI_A_UART_LSB_FIRST,                  // MSB First
        EUSCI_A_UART_ONE_STOP_BIT,               // One stop bit
        EUSCI_A_UART_MODE,                       // UART mode
        EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION  // Oversampling Baudrate
    };
	
	
	
/*		
	EUSCI_A_UART_initParam uartConfig = {
        EUSCI_A_UART_CLOCKSOURCE_SMCLK,          // SMCLK Clock Source
        8,                                       // BRDIV = 8
        14,                                      // UCxBRF = 14
        34,                                      // UCxBRS = 34
        EUSCI_A_UART_NO_PARITY,                  // No Parity
        EUSCI_A_UART_MSB_FIRST,                  // MSB First
        EUSCI_A_UART_ONE_STOP_BIT,               // One stop bit
        EUSCI_A_UART_MODE,                       // UART mode
        EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION  // Oversampling Baudrate
    };
*/
    //WDT_hold(WDT_BASE);

    // Setting the DCO to use the internal resistor. DCO will be at 16.384MHz
//    CS_setupDCO(CS_INTERNAL_RESISTOR);

    // SMCLK should be same speed as DCO. SMCLK = 16.384MHz
    //CS_initClockSignal(CS_SMCLK, CS_CLOCK_DIVIDER_1);	
	
	// use when it is IO
	GPIO_setAsInputPin(PORT_UART, P_UART_RX_Pin);	
	GPIO_selectInterruptEdge(PORT_UART, P_UART_RX_Pin, GPIO_HIGH_TO_LOW_TRANSITION);									 		
	GPIO_clearInterrupt(PORT_UART, P_UART_RX_Pin);
    GPIO_disableInterrupt(PORT_UART, P_UART_RX_Pin);
	
	
	CS_initClockSignal(CS_SMCLK, CS_CLOCK_DIVIDER_2);
    // Settings P1.2 and P1.3 as UART pins.
    GPIO_setAsPeripheralModuleFunctionInputPin(PORT_UART,
                                               P_UART_TX_Pin | P_UART_RX_Pin,
                                               GPIO_PRIMARY_MODULE_FUNCTION);
    // Configure and enable the UART peripheral
    EUSCI_A_UART_init(EUSCI_A0_BASE, &uartConfig);
    EUSCI_A_UART_enable(EUSCI_A0_BASE);

    EUSCI_A_UART_enableInterrupt(EUSCI_A0_BASE,
                                (EUSCI_A_UART_RECEIVE_INTERRUPT));

	//						
	uc_RxBufoffset = 0;

}

void chg_io_to_uartrx_pin(void)
{
	
		GPIO_disableInterrupt(PORT_UART, P_UART_RX_Pin);	
		
		//uart_init();		
		P1SEL0 |=   P_UART_RX;                // P1.2/3 eUSCI_A Function
		P1SEL1 &= ~(P_UART_RX);			
		//UCA0CTL1 |= UCSWRST;                    // Hold eUSCI in reset
		//UCA0CTL1 &= ~UCSWRST;                   // Release from reset
	
}

void chg_uartrx_to_io_pin(void)
{
	P1SEL0 &= ~(P_UART_RX);                
	P1SEL1 &= ~(P_UART_RX);
	GPIO_clearInterrupt(PORT_UART, P_UART_RX_Pin);
    GPIO_enableInterrupt(PORT_UART, P_UART_RX_Pin);	
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=PORT1_VECTOR
__interrupt
#elif defined(__GNUC__)
__attribute__((interrupt(PORT1_VECTOR)))
#endif
void PORT1_ISR(void) {	
	if(uc_action & F_Action_Sleep)
	{
		LPM4_EXIT;		
		chg_io_to_uartrx_pin();
		uc_action &= ~F_Action_Sleep;
	}
}



void change_uart_to_io(void)
{
	GPIO_setAsOutputPin(GPIO_PORT_P1,(P_UART_TX | P_UART_RX));
}
	

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A0_VECTOR
__interrupt
#elif defined(__GNUC__)
__attribute__((interrupt(USCI_A0_VECTOR)))
#endif
void USCI_A0_ISR(void) {
	
	uchr uc_status, uc_data;
	
	if(uc_action & F_Action_Sleep)
	{
		LPM4_EXIT;		
		chg_io_to_uartrx_pin();
		uc_action &= ~F_Action_Sleep;
	}
	
    switch(__even_in_range(UCA0IV, 18))
//      switch(__even_in_range(UCA0IV, USCI_UART_UCTXCPTIFG))
    {
    
		case USCI_UART_UCRXIFG:
                        
			if ((uc_uartflag & F_uart_RxSuccess)==0)
			{
				if((uc_uartflag & F_UARTRxStart)==0)
				{
					uc_uartflag |= F_UARTRxStart;	
					uc_RxBufoffset = 0;			
				}								
				//if(gu8v_UartRxBuf[C_byte1] != 0x55)
				//{
				//	uc_RxBufoffset = 0;			
				//}
				uc_status = OFS_UCAxSTATW;				
				uc_data = EUSCI_A_UART_receiveData(EUSCI_A0_BASE);									
				if((uc_status & (UCOE|UCPE|UCFE|UCRXERR))== 0)
				{
					gu8v_UartRxBuf[uc_RxBufoffset] = uc_data;
                                        uc_RxBufoffset++;
					uc_UART_RxLength = C_UART_TEST_LENGTH;
					if (uc_RxBufoffset >= uc_UART_RxLength)	
					{
						uc_uartflag |= F_uart_RxSuccess;				
											
						//uc_wait_sleep_cnt = C_Wait_Slp_Time;	
					} 					
				}
			}
			
			uc_UART_RxTimoutCnt  = 0;
			uc_wait_sleep_cnt = C_Wait_Slp_Time;
			break;
			
    
		case USCI_UART_UCTXCPTIFG: 
			break;
	  
	  default:
		//case USCI_UART_UCTXIFG:       
		//case USCI_NONE: 
		//case USCI_UART_UCSTTIFG: 
		break;
	
	
    }
}