MSP430F5529: Clock Speed: DCOCLK vs. DCOCLKDIV

/*
 * Set up UCS MCLK for 4 MHz
 * 		Use XT1 (default) for reference FLLRef = 32768 Hz
 * 		Use DCOCLK for MCLK
 * 				D * (N + 1) * FLLRef = Fdco
 * 				D = 1/2
 * 				N = 243
 * 				FLLRef = 32768
 */

#include <msp430.h>

int main(void)
{
	WDTCTL = WDTPW+WDTHOLD;				// Stop WDT

	P1DIR |= BIT0;						// P1.1 output to red LED
	P5SEL |= BIT4 + BIT5;				// select 32768-Hz crystal on P5.4 and pP.5
	P5SEL |= BIT2 + BIT3;				// select 4-MHz crystal on P5.2 and pP.3

	//UCSCTL3 = SELREF__REFOCLK;			// Set DCO FLL reference = REFO (default XT1CLK, but sets fault flag)
	UCSCTL4 |= SELM__DCOCLK;			// Set MCLK = DCOCLK (ACLK default XT1CLK; SELS and SELM default DCOCLKDIV)

	// Loop until XT1 stabilizes
	do
	{
		UCSCTL7 &= ~XT1LFOFFG;
	}while (UCSCTL7 & XT1LFOFFG);		// Test oscillator fault flag

	// Loop until XT2 stabilizes
	do
	{
		UCSCTL7 &= ~XT2OFFG;
	}while (UCSCTL7 & XT2OFFG);			// Test oscillator fault flag

	// set DCO fields and let the FLL work its magic
	__bis_SR_register(SCG0);			// Disable the FLL control loop
	UCSCTL0 = 0x0000;					// Set lowest possible DCOx, MODx
	UCSCTL1 = DCORSEL_4;				// Select DCO range 8MHz operation
	UCSCTL2 |= FLLD__2 + 243;			// Set DCO Multiplier for 8MHz
	                                           //  D  * ( N  + 1) * FLLRef = Fdco
	                                           // 1/2 * (243 + 1) * 32768  = 4.000MHz
	__bic_SR_register(SCG0);			// Enable the FLL control loop

	// Loop until DCO stabilizes
	do
	{
		UCSCTL7 &= ~DCOFFG;
	}while (UCSCTL7 & DCOFFG);			// Test oscillator fault flag

	// Clear overall oscillator fault flag
	SFRIFG1 &= ~OFIFG;					// Clear OFIFG fault flag

	//*************************************************************
	// Blink the LED to check the clock rate
	while(1)
	{
		P1OUT ^= BIT0;
		__delay_cycles(4000000);		// Delay for 1 second at 4 MHz
	}
}