This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR4131: errata cs13 workaround

Part Number: MSP430FR4131

In order to mitigate cs13 with workaround 4, is it enough to set the DCO  to 2 MHz or does it actually have to run at 2 MHz? Assuming, we are running at 16 MHz (DCORSEL = 101b), the following code

bis     #LPM3_bits, 0(SP)
bis     #SCG0, SR
bic     #DCORSEL_4, &CSCTL1
reti

will configure the DCO to 2 MHz but may actually run faster (depending on the DCO bits in CSCTL0). Would it be better to clear with DCORSEL_5 so we configure 1 MHz (which will sure be less than 2 MHz)?

And is it needed to wait some time before the reti?

  • Tom,

    According to workaround description, "Set DCOCLK to 2MHz or lower before entering LPM3/4, then restore DCOCLK after wake-up". It is enough to set the DCO to 2MHz.

    Regards,
    Ling
  • Right. But the errata also says:

    "Device may enter lockup state during transition from AM to LPM3/4 if DCO frequency is above 2 MHz."

    and

    "The device might enter lockup state if DCO frequency is above 2 MHz and two events happen at the same time."

    These two sound as if the actual frequency is crucial, not the nominal one the DCO is set to.

  • Hi Tom,

    It is enough to set the DCO to 2MHz.
    If you still have concern then you can set DCO to 1MHz.
    Thanks.

    Regards,
    Ling
  • Ling Zhu2 said:
    It is enough to set the DCO to 2MHz.

    OK, thanks!

    If you still have concern then you can set DCO to 1MHz.

    Should I have concerns if a TI employee tells me that 2 MHz is OK? ;-)

    Ah, and still unsure about:

    > And is it needed to wait some time before the reti?

  • Hi Tom,

    It it better to add one __nop().

    Regards,
    Ling

**Attention** This is a public forum