MSP430F6779A: ADC Sampling Rate Issue

Part Number: MSP430F6779A
Other Parts Discussed in Thread: MSP-EM-DESIGN-CENTER

Hello All,

Here I have a posted code regarding my problem.

I want to achieve 4.096 sampling frequency but I'm unable to achieve it.

The Sampling frequency = Fm/OSR 

In my code I have a configure Fm is ACLK clock - 32768 Hz

and OSR values I'm changing to achieve 4.096 sampling rate.

Above is my observation on oscilloscope and calculation.

When sampling frequency get increase above 1190.6 Hz it get constant.

So, How I can achieve according to formula/calculation ?

can any one help me to figure out this issue??

#include <msp430f6779a.h>

int bsr_bit=30;

void SD24_B_config(void);

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;   // Stop watchdog timer

    SD24_B_config();

    SD24BCTL1 |= SD24GRP0SC;                // Set bit to start conversion

   __bis_SR_register( GIE);       // Enter interrupt

   for(;;)
   {
   }
}
  
// Sigma-Delta ADC *******************
void SD24_B_config(void)
{
    SD24BCTL0 = SD24REFS | SD24SSEL_2 ;      // Select internal REF // Select SMCLK as SD24_B clock source

    SD24BOSR0 = bsr_bit;        //C7 for 5K samplin; OSR = 520
    SD24BOSR1 = bsr_bit;        //C7 for 5K samplin; OSR = 520
    SD24BOSR2 = bsr_bit;        //C7 for 5K samplin; OSR = 520
    SD24BOSR3 = bsr_bit;        //C7 for 5K samplin; OSR = 520
    SD24BOSR4 = bsr_bit;        //C7 for 5K samplin; OSR = 520
    SD24BOSR5 = bsr_bit;        //C7 for 5K samplin; OSR = 520
    SD24BOSR6 = bsr_bit;        //C7 for 5K samplin; OSR = 520

    SD24BCCTL0 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
    SD24BCCTL1 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
    SD24BCCTL2 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
    SD24BCCTL3 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
    SD24BCCTL4 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
    SD24BCCTL5 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
    SD24BCCTL6 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0

    SD24BIE = SD24IE5;                      // Enable channel 5 interrupt
}

// 24Bit ADC Interrupt Sub routine
#pragma vector=SD24B_VECTOR
__interrupt void SD24BISR(void)
{
    P1DIR |=BIT4;
    P1OUT ^= BIT4;  // for debug
    if(SD24BIV == SD24BIV_SD24IFG5)
    {
        Ch0results = SD24BMEMH0 
        Ch4results = SD24BMEMH4

        Ch1results = SD24BMEMH1 
        Ch5results = SD24BMEMH5

        Ch2results = SD24BMEMH2
        Ch6results = SD24BMEMH6

        Ch3results = SD24BMEMH3 

        }
    }
}

Regards,

Kelvin