MSP430FR2355: MSP430FR2355 SPI problems

To be clear, when you refer to idle state do you mean the period when the eUSCI is blocked waiting for the next character to be written to TXBUF?

As I understand it, the state of MOSI will only change on the appropriate edge of the bit clock, as selected by the UCCKPL and UCCKPH. In your trace that's the falling edge of CLK. Between characters the bit clock is inactive, so MOSI is held at the value of the last bit transmitted.

This doesn't matter from the point of view of the slave device, but if you have a long delay between characters it might increase power consumption.

I don't think there's a way around that within the eUSCI peripheral itself. You could switch the MOSI pin back to GPIO mode at the appropriate level between transfers, however.

EDIT: Yes, that works. I configured P1.7 GPIO as input with pulldown, then selected eUSCI before loading each byte and set back to GPIO after RXIFG:

Note that a short delay is required after RXIFG to ensure that the slave has definitely finished reading before the state of MOSI is changed. This needs to last at least 1/2 of a bitclock cycle.