MSP430FR5994: Testing SVSH and clock save.

Hi,

As described in section 1.2 System Reset and Initialization of the User's Guide, SVSH low condition will trigger a BOR reset for device. All the registers of RTC should be reset after a BOR.

Is this a Rev. B hardware bug.  Rev. C silicon might behave correctly.

This comes down to a documentation error.  The errata documents should include chapters for older revisions of silicon.  There is currently no way to determine this issue from the current versions of the documentation.

If it is TI policy only to describe the latest revision, the prior versions of the errata documents should be made available for download so that issues such as this can be resolved.

I can confirm that the clock read also fails with the Rev. C silicon after further testing: 

Here is the code extract (in Mecrisp Forth:)

  case
    $0E of                              \ SVSH == $0E ?
\     LOCKLPM5 PM5CTL0 PMMBase + bic!   \ clear.b LOCKLPM5
      RTCCNT12 RTCBASE + @ Epoch0-LL !  \ Epoch0-LL.w = RTCCNT12
      RTCCNT34 RTCBASE + @ Epoch0-HH !  \ Epoch0-HH.w = RTCCNT34
      true TRAPDOOR !                   \ clear trapdoor
      2 TEMP +!                         \ inc temp
      begin dup sec? = until            \ wait 256 s for bor
      swbor ( -- na )                   \ terminate program flow
    endof

The LOCKLPM5 is commented out.

I can confirm that the "clear trapdoor" code is executed.

The tests were performed in active mode.  I will retest for lpm3.5 as soons as we have concluded the active mode issue.

Here is the counter setup:

  PWD_RTC  RTCBASE RTCPWD  + c!         \ unlock
  RTCSSEL  RTCBASE RTCCTL1 + c!         \ setup counter mode.
  RT0PSDIV RTCBASE RTCPS0CTL + !
  RT1SSEL RT1PSDIV + RT1IP + RTCBASE RTCPS1CTL + !
  RTCHOLD RTCBASE RTCCTL1 + cbic!       \ clear the RTCHOLD and bit to start the counter.
  0 RTCBASE RTCPWD + c!                 \ lock