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CCS/MSP430F5419A: XT1 current in LMP4

Part Number: MSP430F5419A

Tool/software: Code Composer Studio

Hi, I have a board which has an external 16Mhz crystal on XT1.

I have code which runs this board either from the internal DCO @ 16Mhz or using the external xtal.

When configured for the external oscillator i'm getting about 350uA more current when in LMP4 mode than with the internal DCO.

Is there something I should be doing to turn off the XT1 before going into LMP4?

void InitXTAL(void)
{
	//Set Up Vcore Voltage Level 2 up to 20Mhz
	PMM_setVCore(PMM_CORE_LEVEL_2);

#ifdef INT_XTAL
	//Configure XTAL IO
	GPIOConfigOutputLow(IO_XTAL_XT1_XIN); //XT1 Output Low
	GPIOConfigOutputLow(IO_XTAL_XT1_XOUT); //XT1 Output Low

	UCSCTL3 = SELREF__REFOCLK;    // FLL: REFO
	UCSCTL4 = SELA__REFOCLK | SELS__DCOCLK | SELM__DCOCLK; //ACLK: REFO, SMCLK: DCO, MCLK: DCO
	UCSCTL5 = DIVS__2; //SMCLK: /2
	UCSCTL6 = XT1OFF | XT2OFF;    // turn off XT1 and XT2

	// Initialize DCO to 16.00MHz
	__bis_SR_register(SCG0);		// Disable the FLL control loop

	UCSCTL0 = 0x0000u;				// Set lowest possible DCOx, MODx
	UCSCTL1 = DCORSEL_7;			// Set RSELx for DCO = 50 MHz
	UCSCTL2 = 488u;					// Set DCO Multiplier for 16MHz
									// (N + 1) * FLLRef = Fdco
									// (488 + 1) * 32768 = 16MHz

	__bic_SR_register(SCG0);		// Enable the FLL control loop

	// Worst-case settling time for the DCO when the DCO range bits have been
	// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
	// UG for optimization.
	// 32*32*16MHz/32768Hz = 500000 = MCLK cycles for DCO to settle
	__delay_cycles(500000u);

#else //Ext XTAL
    //Config XTAL IO
	GPIODirInput(IO_XTAL_XT1_XIN); //Input
	GPIODirOutput(IO_XTAL_XT1_XOUT); //Output
	GPIOPeripheralEnable(IO_XTAL_XT1_XIN); 	//Set XIN as peripheral function which is XT1
	GPIOPeripheralEnable(IO_XTAL_XT1_XOUT);	//Set XOUT as peripheral function which is XT1

        //Enable XT1 with mid drive strength
	UCSCTL6 = XTS | XT1DRIVE_1 | XT2OFF;
	//XTAL = 16MHz - MCLK 16MHz - SMCLK 8MHz
	UCSCTL4 = SELA__REFOCLK | SELS__XT1CLK | SELM__XT1CLK; //ACLK: REFO, SMCLK: XT1, MCLK: XT1
	UCSCTL5 = DIVS__2; //SMCLK: /2



#endif

	//Make sure ACLK stays on all the time
	BitSet(UCSCTL8,  ACLKREQEN);

	/* Loop until XT1,XT2 & DCO fault flag is cleared */
	do
	{
		// Clear XT2,XT1,DCO fault flags (Reset if still in fault)
		BitClear(UCSCTL7, (XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG));
		// Clear Oscillator fault flags
		BitClear(SFRIFG1, OFIFG);
	}
	while (BitTest(SFRIFG1,OFIFG)); //Test oscillator fault flag
}

  • Hi Steven,
    there are a few things in your code, which you need to check.
    The first thing are the two code lines
    GPIODirInput(IO_XTAL_XT1_XIN); //Input
    GPIODirOutput(IO_XTAL_XT1_XOUT); //Output
    When looking into the datasheet of this device, in Table 6-51 you can find the necessary settings for XT1 function selection.
    The P7DIR.x control bits are don't care. P7SEL.0 need to be set in both cases Xin/Xout, and XT1BYPASS needs to be cleared to 0.
    So you need to check whether this is happening on
    GPIOPeripheralEnable(IO_XTAL_XT1_XIN); //Set XIN as peripheral function which is XT1
    GPIOPeripheralEnable(IO_XTAL_XT1_XOUT); //Set XOUT as peripheral function which is XT1
    execution, but the GPIODir... instructions are useless.
    In case of the ACLK, you're selecting the REFO as clock source and enable clock request, the comment says "make sure ACLK stays on all the time". Now the nature of LPM4 would be shutting down all clock sources and oscillators, so why are you trying to go to LPM4, while forcing the device to keep REFO and ACLK active?
    The current consumption is an effect of active/non-active modules of the device. Also with the XT1, when intending to switch with the high frequency oscillator to LPM4, you should disable it. Unlike the DCO, which is deactivated in LPM3 if not used for a clock domain, in LPM4 in any case shut down, this is not the case with XT1 in high frequency mode.

    Best regards
    Peter
  • Hi, GPIOPeripheralEnable sets the P7SEL.0 and P7SEL.1 bits. XT1BYPASS is cleared on Line 41 when UCSCTL6 is set.

    I am using ACKL to run a timer (TA0) to wake the processor back up so it needs to run all the time.

    How should I disable the XT1 oscillator? like this?

    BitSet(UCSCTL6, XT1OFF);
    __bis_SR_register(LPM4_bits); // Enter LPM4

    Do I need to re-enable it after?

    I understand having aclk running will cost current. What I don't currently understand is why XT1 being selected over using the DCO / FLL takes 350uA more current.

    My board sits in LPM4 at 320uA when INT_XTAL is defined and 670uA when it is commented out. This does not seem correct. The high power is other parts of my board, I'm just interested in the differential between internal and external.
  • Hi Steven,
    in relation to the LPM4, I was just trying to say, it does probably not make much difference, whether you set the LPM4 or LPM3, as long as you force the MSP to keep the ACLK alive in the LPM4. It is kind of unusual thing to do, and it's sometimes risky using things in a way, which they have not been intended for.
    In terms of the XT1 deactivation, the setting of the XT1OFF should be sufficient for disabling the oscillator in any mode.
    Yes, in the moment you need the clock from XT1 again, or better to say before, you need to restart it, by clearing the XT1OFF again. You need to consider the startup time of the oscillator, which is heavily dependent on the HW setup of yours and the used crystal. Also the drive level you have selected for the XT1 is having a major impact.
    If understand you comments correctly, if the internal DCO with FLL is selected, the current consumption is lower than with the XT1, correct?
    While the selected frequency is the same (according to your comments), you're not necessarily operating the DCO at the 16MHz.
    You're disabling the FLL by
    __bis_SR_register(SCG0); // Disable the FLL control loop
    The DCO in the F5xx and F6xx family is pretty inaccurate itself. That's why we have in these families the FLL clock system integrated, to support by using a reference clock source, typically a 32.768kHz crystal, to stabilize the DCO using the FLL.
    Looking into the data sheet with the lowest modulation bits
    UCSCTL0 = 0x0000u; // Set lowest possible DCOx, MODx
    and
    UCSCTL1 = DCORSEL_7; // Set RSELx for DCO = 50 MHz
    the possible DCO frequency range is 8.5MHz - 19.6MHz. So potentially you could be at half the clock speed with the DCO compared to XT1 at 16MHz.
    Also not sure why you commented being at 50MHz. I would always recommend checking the actual clock by switching the respective clock to a pin and measuring the signal with a scope. The second recommendation would be definitely operating the DCO with active FLL. Otherwise your MSP code execution performance, timings, currents might vary quite a lot from device to device and over temperature. That's what one usually doesn't want to have.
    To really check whether the current consumption values are resulting from the clock source selection and not from other things, I would recommend creating small test codes, derived from our code examples, but difficult to comment on necessary modifications, as I do not know your HW. Basically you need to terminate all unused GPIOs to avoid floating nodes, switch the clock source to the SMCLK output pin and switch the device to LPM0, while measuring the current consumption.
    Please also keep in mind the current consumption with a crystal oscillator is dependent on the crystal (ESR and load capacitance) and your HW design.
    I hope this helps a bit more.

    Best regards
    Peter
  • Hi Steven,
    do you still need support on this? I assume your questions have been answered sufficiently, thus I am closing the thread, but if there should still be questions on your side, you can re-open it.

    Best regards
    Peter

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