MSP430G2553: P1IFG Extraneous Bits Being Set!

BrentF

Part Number: MSP430G2553

There is only one pin configured for input on P1, and interrupts are only enabled for that one pin. The interrupt handler is only called on a high-low transition of that input pin, exactly as configured.

However... there are several other bits also set in P1IFG. Even if they are cleared, the next time the interrupt handler is entered, they are all set again (bits 0, 3, 6, and 7).

What can cause this, other than setting them in software?

Port Config:

#define ENABLE_BTN_PIN 3
#define ENABLE_BTN (1 << ENABLE_BTN_PIN)

P1IES = ENABLE_BTN; // input: edge select High->Low
P1IE = ENABLE_BTN; // input: generate interrupts on input change
P1REN = ENABLE_BTN; // enable resistor
P1OUT |= ENABLE_BTN;// pull-up

over 7 years ago

0 Bruce McKenney over 7 years ago

Guru 103195 points

This is routine. The IFG bits reflect activity on the pins, independent of the IE bits. The IE bits allow the (corresponding) IFG bits to generate an interrupt request.

0 BrentF over 7 years ago in reply to Bruce McKenney

Prodigy 70 points

That would explain it. But even when the pins are configured as outputs?

0 Bruce McKenney over 7 years ago in reply to BrentF

Guru 103195 points

[Ref User Guide (SLAU144J) Sec. 8.2.7.1-2]
[Ref Data Sheet (SLAS735J) Port Schematics, (e.g.) p. 42]

0 BrentF over 7 years ago in reply to Bruce McKenney

Prodigy 70 points

Thank you. That explains it.

But it's still a surprising gotcha.
> NOTE: PxIFG Flags When Changing PxOUT or PxDIR
> Writing to P1OUT, P1DIR, P2OUT, or P2DIR can result in setting the corresponding P1IFG
or P2IFG flags.

In other words, all bits of PxIFG should be considered random garbage, except for only those Input pins explicitly enabled in PxIE.

0 Bruce McKenney over 7 years ago in reply to BrentF

Guru 103195 points

> In other words, all bits of PxIFG should be considered random garbage, except for only those Input pins explicitly enabled in PxIE.

I guess that's one way of saying it. This is generally true of the MSP430 IFG bits: The IFG indicates that some event happened -- whether you were watching or not -- and the IE causes the IFG to have some effect. As a consequence, you should (almost) always clear an IFG before setting its IE.

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MSP430G2553: P1IFG Extraneous Bits Being Set!