- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
Part Number: MSP432P4111
Tool/software: TI-RTOS
Hi all,
I'm having trouble starting and using the LFXT.
The code below shows how I setup and start the SimpleLink Power Manager. In particular, I want BCLK to be sourced from the LFXT to ensure good timing keeping from the RTC. I also set ACLK to run from from the LXFT.
I find that sometimes the device starts up with the LFXTIFG flag is set and ACLK & BCLK by implication are running from REFO. This is not what I want!
I say by implication because there is no register that indicates the current source of ACLK/BCLK. If there is an error with LFXT the MSP432 fallbs back to REFO but leaves the registers as they were - the failover seems to be silent except for the LFXTIFG flag.
While LXFTIFG is set, P4.2 (setup to output ACLK) gives a waveform that is close to (but not quite exactly) 32768Hz with a fair bit of timing jitter. When LXFTIFG is clear, P4.2 is dead stable and dead on 32768Hz.
I've setup a task to periodically check and clear LXFTIFG as a precaution but I'd rather the RTOS looked started up the LXFT reliably.
Is there something wrong with my setup? Am I missing part of the process?
Using CCS 9.01, Compiler 18.12.1.LTS, SimpleLink 2.2
#define NUMCUSTOMPERFLEVELS 1
PowerMSP432_PerfLevel customPerfLevels[NUMCUSTOMPERFLEVELS] = {
{
.activeState = PCM_AM_LDO_VCORE1, // LDO rather than DCDC to reduce ADC noise
.VCORE = 1,
.DCORESEL = CS_DCO_FREQUENCY_48,
.SELM = CS_DCOCLK_SELECT,
.DIVM = CS_CLOCK_DIVIDER_1,
.MCLK = 48000000,
.DIVHS = CS_CLOCK_DIVIDER_1,
.HSMCLK = 48000000,
.SELS = CS_DCOCLK_SELECT,
.DIVS = CS_CLOCK_DIVIDER_2,
.SMCLK = 24000000,
.SELA = CS_LFXTCLK_SELECT, // Since we already use XTAL for BCLK, use it for ACLK too (rather than REFO)
.DIVA = CS_CLOCK_DIVIDER_1,
.ACLK = 32768,
.SELB = CS_LFXTCLK_SELECT, // Use XTAL so that RTC timekeeping is reasonably accurate
.BCLK = 32768,
.flashWaitStates = 3,
.enableFlashBuffer = true,
},
};
const PowerMSP432_ConfigV1 PowerMSP432_config =
{
.policyInitFxn = &PowerMSP432_initPolicy,
.policyFxn = &PowerMSP432_sleepPolicy,
// The performance levels defined in PowerMSP432.c take indices 0..3. Our custom level takes index 4
.initialPerfLevel = 4,
.enablePolicy = false,
.enablePerf = true,
.enableParking = true,
.customPerfLevels = customPerfLevels,
.numCustom = NUMCUSTOMPERFLEVELS,
.useExtendedPerf = true,
// Don't use HFXT
.configurePinHFXT = false,
.HFXTFREQ = CS_48MHZ,
.bypassHFXT = false,
.configurePinLFXT = true,
.LFXTDRIVE = CS_LFXT_DRIVE3,
.bypassLFXT = false,
// Don't use the interrupt
.enableInterruptsCS = false,
.priorityInterruptsCS = CS_INTERRUPT_PRIORITY,
.isrCS = CS_HWI,
};
main()
{
Power_init();
// Other startup stuff
BIOS_start();
}
G'Day Chris,
(1) Yes, CS.CSCTL2.LFXTDRIVE = 3 (which is as configured by the .LFXTDRIVE field of PowerMSP432_config above). This is the power up default setting for the device, so I guess its a "safe" setting. The datasheet is not very clear about how to set this. Once we adjust our load capacitors (see point 2) we get the most accurate clock rate (as measured at P4.2, setup to output ACLK) with a drive of 3. Gets worse if drive is lower even though the info from the datasheet (attached below) seems to say any setting from 1..3 should work.
Do you have any advice on how to set this? Is it possible to overdrive the oscillator by setting the drive strength too high? Any other traps for young players?
(2) Using the calculation in note 6, page 53 of the datasheet (SLASEA0B).
We have a 6pF oscillator and 8pF capacitors, which (assuming Clfxin = Clfxout = 2pF per datasheet) gives a effective load capacitance of 10 x 10 / (10+10) = 5pF.
Close, slightly low.
Increasing the caps to 10pF (for an effective load capacitance of 6pF) seems to improve frequency accuracy (with drive strength of 3). Will do some tests and see if it helps with the startup problems.
(3) Yes, I think so. The layout is below. There is 5mm from the middle of the oscillator to the middle of the pads. You can see vias through to ATE pads on the bottom of the PCB. For what its worth, there is a reasonably solid ground plane under the micro, and a metal can over the micro and the oscillator.
(4) The failures we have observed have all been at startup.
Cheers
Julian
**Attention** This is a public forum
