MSP430FR6047: LFXTCLK

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//******************************************************************************
//   MSP430FR60xx Demo - Using LFXT in bypass mode, failsafe operation shown
//
//   Description: ACLK is sourced from LFXT configured in bypass mode.
//   An external 32768 Hz digital input signal is required for this example.
//   When the signal is removed, ACLK defaults to LFMODOSC = 5MHz/128
//   The LED blinks as long as the fault condition remains.
//   Once the fault is fixed, LED goes OFF and ACLK is restored back to the
//   digital input.
//
//   ACLK = External digital in 32kHz, MCLK = SMCLK = 1MHz
//
//           MSP430FR6047
//         ---------------
//     /|\|               |
//      | |               |
//      --|RST            |
//        |               |
//        |      PJ.4/XIN |<-- External 32768Hz required!
//        |          P7.0 |--->ACLK
//        |          P1.0 |--->LED
//
//   Cameron P LaFollette
//   Texas Instruments Inc.
//   November 2017
//   Built with IAR Embedded Workbench V7.10 & Code Composer Studio V7.2
//******************************************************************************
#include <msp430.h>

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;

    // Configure GPIO
    P1OUT = 0;
    P1DIR |= BIT0;                          // LED setup

    P7DIR |= BIT0;
    P7SEL0 &= ~BIT0;                         // Output ACLK
    P7SEL1 |= BIT0;

    PJSEL0 |= BIT4;

    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    // XT1 Setup
    CSCTL0_H = CSKEY_H;                     // Unlock CS registers
    CSCTL1 = DCOFSEL_0;                     // Set DCO to 1MHz
    CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // Set all dividers
    CSCTL4 = LFXTBYPASS | HFXTOFF | LFXTOFF;

    do
    {
        CSCTL5 &= ~LFXTOFFG;                // Clear XT1 fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag

    // Now that osc is running enable fault interrupt
    SFRIE1 |= OFIE;

    __bis_SR_register(LPM0_bits | GIE);     // Wait in LPM0 for fault flag
    __no_operation();
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=UNMI_VECTOR
__interrupt void UNMI_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(UNMI_VECTOR))) UNMI_ISR (void)
#else
#error Compiler not supported!
#endif
{
    do
    {
        // set a breakpoint on the line below to observe XT1 operating from LFMODOSC
        // when the breakpoint is hit during a crystal fault
        CSCTL5 &= ~LFXTOFFG;                // Clear XT1 fault flag
        SFRIFG1 &= ~OFIFG;
        P1OUT ^= BIT0;
        __delay_cycles(25000);              // time for flag to get set again
    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag

    P1OUT &= ~BIT0;
}