MSP430FR6989: Default SMCLK frequency

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 * demonstrate a single peripheral function or device feature in a highly
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 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
 * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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//******************************************************************************
//   MSP430FR69xx Demo - Output 32768Hz crystal on XT1 and observe failsafe
//
//   Description: Configure ACLK = LFXT1 and enter LPM3.
//   To observe failsafe behavior short the crystal briefly on the target board.
//   This will cause an NMI to occur. P1.0 is toggled inside the NMI ISR.
//   Once the fault flag is cleared XT1 operation continues from 32768Hz crystal
//   Otherwise ACLK defaults to LFMODCLK (~37.5KHz).
//   ACLK = LFXT1 = 32kHz, MCLK = SMCLK = 1MHz
//
//           MSP430FR6989
//         ---------------
//     /|\|            XIN|-
//      | |               | 32KHz Crystal
//      --|RST        XOUT|-
//        |               |
//        |           P5.2|---> ACLK = 32.768kHz (or 37.5kHz during LFXTOFFG)
//        |           P7.4|---> SMCLK = MCLK = 1MHz
//        |           P1.0|---> LED
//
//   William Goh
//   Texas Instruments Inc.
//   April 2014
//   Built with IAR Embedded Workbench V5.60 & Code Composer Studio V6.0
//******************************************************************************
#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;

  // GPIO Setup
  P1OUT = 0;
  P1DIR = BIT0;                             // For LED

  P5DIR |= BIT2;
  P5SEL0 |= BIT2;                           // Output ACLK
  P5SEL1 |= BIT2;

  P7DIR |= BIT4;
  P7SEL0 |= BIT4;
  P7SEL1 |= BIT4;                           // Output SMCLK

  PJSEL0 = BIT4 | BIT5;                     // For XT1

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // Clock System Setup
  CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers
  CSCTL1 = DCOFSEL_0;                       // Set DCO to 1MHz
  CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
  CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;     // Set all dividers
  CSCTL4 &= ~LFXTOFF;
  do
  {
    CSCTL5 &= ~LFXTOFFG;                    // Clear XT1 fault flag
    SFRIFG1 &= ~OFIFG;
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  // Now that osc is running enable fault interrupt
  SFRIE1 |= OFIE;

  __bis_SR_register(LPM0_bits);             // Wait in LPM0 for fault flag
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=UNMI_VECTOR
__interrupt void UNMI_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(UNMI_VECTOR))) UNMI_ISR (void)
#else
#error Compiler not supported!
#endif
{
  do
  {
    // set a breakpoint on the line below to observe XT1 operating from VLO
    // when the breakpoint is hit during a crystal fault
    CSCTL5 &= ~LFXTOFFG;                    // Clear XT1 fault flag
    SFRIFG1 &= ~OFIFG;
    P1OUT |= BIT0;
    __delay_cycles(25000);                  // time for flag to get set again
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  P1OUT &= ~BIT0;
}