Other Parts Discussed in Thread: TCA9548A, MSP430WARE
Tool/software: Code Composer Studio
Hi ,
we are using one zcu111 xilinx rfsoc board .This board have a system controller mcu MSP430F5342 .Ther is a i2c mux (tca9548a) from ti in it, which have 8 channels and I am trying to programme it through MSP430F5342 .I am trying to enable channel 1 in this i2c mux for that I have taken one master receiver example i2c code given from ti (MSP430F534x_uscib0_i2c_10.c) only by modifying slave address . The tca9548a address is 0x74 .According to the datasheet it have only one control register which can be read by giving the slave address with read bit as set . I am trying to read the control register but not able to
I have seen some of the post where they are telling to right shift the slave address by 1 bit as the USCI module will take this by shifting it to 1 bit left automatically . I didn't get this point but still I have tried with 2 addresses 0x74 and 0x3A (by right shifting 0x74) . Issue I am facing is the UCRXIFG is not setting up at all and the isr is not executing so am I not able to read the UCB0RXBUF. I have attached my code here .Can any one explain what is the problem and where I am going wrong and shifting the slave address is it necessary ?.
Same issue I am facing while configuring the msp430 to master transmitter also . When I an trying to send tx data to UCB0TXBUF , not acknowledgement (UCNACKIFG) flag is always high .
#include <msp430.h>
unsigned char *PRxData; // Pointer to RX data
unsigned char RXByteCtr;
volatile unsigned char RxBuffer[128]; // Allocate 128 byte of RAM
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= 0x03; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x74; // Slave Address
// UCB0I2CSA = 0x3A;
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCRXIE; // Enable RX interrupt
while (1)
{
PRxData = (unsigned char *)RxBuffer; // Start of RX buffer
RXByteCtr = 1; // Load RX byte counter
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0CTL1 |= UCTXSTT; // I2C start condition
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
// Remain in LPM0 until all dat a
// is RX'd
__no_operation(); // Set breakpoint >>here<< and
} // read out the RxBuffer buffer
}
//-------------------------------------------------------------------------------
// The USCI_B0 data ISR is used to move received data from the I2C slave
// to the MSP430 memory. It is structured such that it can be used to receive
// any 2+ number of bytes by pre-loading RXByteCtr with the byte count.
//-------------------------------------------------------------------------------
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCB0IV,12))
{
case 0: break; // Vector 0: No interrupts
case 2: break; // Vector 2: ALIFG
case 4: break; // Vector 4: NACKIFG
case 6: break; // Vector 6: STTIFG
case 8: break; // Vector 8: STPIFG
case 10: // Vector 10: RXIFG
RXByteCtr -- ; // Decrement RX byte counter
if (RXByteCtr)
{
*PRxData++ = UCB0RXBUF; // Move RX data to address PRxData
if (RXByteCtr == 1) // Only one byte left?
UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition
}
else
{
*PRxData = UCB0RXBUF; // Move final RX data to PRxData
__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
}
break;
case 12: break; // Vector 12: TXIFG
default: break;
}
}
Regards,
Soumya
