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Original question:

MSP430F4784: 16-bit sigma-delta ADC question

MSP430F4784: Creating a Custom-BSL

Takayuki Miyazaki
Genius 10120 points
Part Number: MSP430F4784
Other Parts Discussed in Thread: MSPBSL

Hi team,

I got some inquiries about ""Creating a Cusom BSL". Customer seems to investigate custom BSL for MSP430. Customer is referring to this document(https://www.ti.com/lit/an/slaa450g/slaa450g.pdf) and MSPBSL_CustomBSL430 1_01_00_01(https://www.ti.com/tool/MSPBSL).

1. Section 1.2 Device Start-up Sequence

Regarding the operation from "Set PC to addr @0x17F2" to "BSL Protect Function returns 0x02 in R12?", customer understands the switching the code to be executed according to the value of R12. Also, Customer understand that it is same behavior as the judgment of 0x17F4 and 0x17F6. Is that correct?

2. BSL430_Low_Level_Init.asm

Regarding above "Figure 1. Device Start-up Sequence", customer would like to understand what " Set PC to addr @ 0x17FA(BSL Runs " means. Since the following description was defined at "0x17FA". That means, code is starting from 0x1000. Is that correct?

> BslEntryLoc     .word       BSL_Entry_JMP

3. As the result, "JMP   C_Branch" is executed. After that, main(void) is carried out in BSL430_Command_Interpreter.c file. Is that correct? 

 

BSL_Entry_JMP JMP   C_Branch                   ; BSL ENTRY AREA
               JMP   BSL_ACTION0
               JMP   $                         ;BSL_ACTION1 unused
               JMP   $                         ;BSL_ACTION2 unused
               JMP   $                         ;BSL_ACTION3 unused
 C_Branch     BR     #_c_int00                 ;BSL_ACTION4 unused

4. Regarding above " JMP   BSL_ACTION0", When is the code executed?

5. Regarding those assembly-code, would you share helpful documents/URl with customer, please? Customer was looking for it, however, they were not able to find it.

6. Especially, customer was looking for reference-manual for "RETA" command. Although They already checked " MSP430 Assembly Language Tools " document(https://www.ti.com/lit/ug/slau131v/slau131v.pdf), there is not any description for this.Could you clarify it, please ?

 

Best regards,

Miyazaki

  • 0
    Guru 34483 points

    Just to make things clear, costumer should refer to 2xx flash family BSL documentation and related code, because F4xx BSL is related to 2xx flash family, not to 5xx / 6xx. RETA is related to CPUvX2 (20-bit addressing on F5xx/F6xx and FRAM family).

  • 0
    TI__Mastermind 23065 points

    Hi Miyazaki

    I answer the 1st question as the following:

    Q1. Section 1.2 Device Start-up Sequence

    Regarding the operation from "Set PC to addr @0x17F2" to "BSL Protect Function returns 0x02 in R12?", customer understands the switching the code to be executed according to the value of R12. Also, Customer understand that it is same behavior as the judgment of 0x17F4 and 0x17F6. Is that correct?

    A1:

    Switch the code according to the value of R12. 

    the judgment point is 0xC35A@0x17F6 AND 0x3CA5 @0x17F4.

    0x17F6: BSL Unlock Signature 1. This word should be set to 0xC35A to indicate a correctly programmed BSL. If it is written with any other value, the BSL will not start.
    0x17F4: BSL Unlock Signature 2. This word should be set to 0x3CA5 to indicate a correctly programmed BSL. If it is written with any other value, the BSL will not start.

    Thanks!

  • 0 in reply to Xiaodong LI
    TI__Genius 10120 points

    Hello Xiaodong,

    Thanks for your clarification about #1 question.

    Regarding #6, I noticed TI releases “CPUX” document (https://www.ti.com/lit/ug/slau391f/slau391f.pdf). This document is addressing on F5xx/F6xx, as zrno mentioned above. However, this explains the RETA instruction. Therefore, I will share this information with customer

    Regarding #2 - #5, I’m not familiar with assemble code… it will be appreciated if you will share any Expert’s comments on them.

    Best regards,

    Miyazaki

  • 0 in reply to Takayuki Miyazaki
    TI__Mastermind 23065 points

    Hi Miyazaki

    >> Regarding #6, I noticed TI releases “CPUX” document (https://www.ti.com/lit/ug/slau391f/slau391f.pdf). This document is addressing on F5xx/F6xx, as zrno mentioned above. However, this explains the RETA instruction. Therefore, I will share this information with customer

    RETA is the Extended Emulated Instructions of MSP430X CPU, please find the description of RETA on page 284 of MSP430x4xx Family User's Guide (Rev. L)

    >> 2. BSL430_Low_Level_Init.asm

    Regarding above "Figure 1. Device Start-up Sequence", customer would like to understand what " Set PC to addr @ 0x17FA(BSL Runs " means. Since the following description was defined at "0x17FA". That means, code is starting from 0x1000. Is that correct?

    0x17FA is BSL Start Vector. This is the address of the first instruction to be executed when the BSL starts.

    The Z-Area is a section of BSL memory between addresses 0x1000 and 0x100F that can be jumped to and read from external application code. 0x1000 is not the entry of ROM based BSL. it should be the entry of customized flash based BSL.

  • 0 in reply to Xiaodong LI
    TI__Mastermind 23065 points

    Hi Miyazaki

    After discussed BSL expert:

    https://www.ti.com/lit/an/slaa450g/slaa450g.pdf is for 5xx, 6xx, G2.  the diagram we have (the one that I attached) only belong for the F5xx and F6xx family. the address 0x1000h is the where the original BSL located for the F5xx and F6xx family which is info flash and it is programmable.

    According to User’s Guide MSP430™ Flash Devices Bootloader (BSL), page 4, Table 1-1. BSL Overview, the MSP430F4xx BSL is ROM (0xC00h) which is not programmable.

  • 0 in reply to Xiaodong LI
    TI__Genius 10120 points

    Hi Xiaodong,

    Thank you for your clarification. I shared your advice/comments with customer. I appreciate your strong help !

    Best regards, Miyazaki

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