MSP432P401R: 32-Bit DMA over SPI

awu@seantec

Part Number: MSP432P401R

My goal is to achieve an I2S-compatible PCM-audio transfer using SPI and an external Codec (Maxim 9867). Main concept is:

Short audio sample is located in memory
Have a timer providing the frame sync signal
Use SPI to feed the digital audio interface
Configure DMA with timer as trigger to transfer 4 bytes:
- 2 bytes (16 bits) left channel
- 2 bytes for right channel (according to I2S specification)

Hence I setup TIMER_A3 with period of 543 ticks according to audio sampling frequency of 44.1 kHz. This does produce a proper frame sync signal visible in logic analyzer. The SPI on EUSCI_B1_BASE is configured properly (we will see later). So far so good...

Then I use the TIMER_A3_CCR0 as trigger for DMA_CH6 which leads to the following source code for DMA:

#define MAXIM_PLAY_DMA_CHANNEL         DMA_CH6_TIMERA3CCR0
#define MAXIM_PLAY_DMA_CH_NUMBER       DMA_CHANNEL_6
#define AUDIO_BUFFER_SIZE				0x10

#define DMA_ARBITRATION_VALUE   UDMA_ARB_2

volatile uint8_t audioBuffer[2 * AUDIO_BUFFER_SIZE];

/* Later audioBuffer will be parameter of this function */
void maximPlayDMAinit(volatile uint8_t * pData)
{
   MAP_DMA_disableChannel(MAXIM_PLAY_DMA_CH_NUMBER);
   MAP_DMA_assignChannel(MAXIM_PLAY_DMA_CHANNEL);
   MAP_DMA_disableChannelAttribute(MAXIM_PLAY_DMA_CHANNEL
                                   , UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK
                                   );
   MAP_DMA_setChannelControl(MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT
                         , UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | DMA_ARBITRATION_VALUE
                         );
   MAP_DMA_setChannelControl(MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT
                         , UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | DMA_ARBITRATION_VALUE
                         );
   MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)pData
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)(pData + AUDIO_BUFFER_SIZE)
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   MAP_DMA_clearInterruptFlag(MAXIM_PLAY_DMA_CH_NUMBER);
}

void maximStartPlayDMA()
{
   MAP_DMA_clearInterruptFlag(mPlayDMAconfig.channelNumber);
   MAP_DMA_assignInterrupt(DMA_INT1, mPlayDMAconfig.channelNumber);
   MAP_DMA_enableChannel(mPlayDMAconfig.channelNumber);
   MAP_Interrupt_enableInterrupt(INT_DMA_INT1);
   MAP_DMA_enableInterrupt(DMA_INT1);
}

void dma_1_interrupt(void)
{
   uint32_t ui32Mode = MAP_DMA_getChannelMode( MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT);
   if (ui32Mode == UDMA_MODE_STOP)
   {
      /* Ping Pong Primary */
      fill_buf(audioBuffer);
      MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)audioBuffer
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   }
   ui32Mode = MAP_DMA_getChannelMode( MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT);
   if (ui32Mode == UDMA_MODE_STOP)
   {
      /* Ping Pong Secondary */
      fill_buf(audioBuffer + AUDIO_BUFFER_SIZE);
      MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)(audioBuffer + AUDIO_BUFFER_SIZE)
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   }
}

When I give it a try I can see the audio samples in logic analyzer in right order, but there are only 2 Bytes being transfered upon each trigger from frame sync signal: (please disregard the last 8 not matching bits in decoded data as a configuration issue - the signals are the same, obviously):

Of course, you might say, I simply need to change the define to UDMA_ARB_4. But this is where the real odds (and major topic of this post) are coming up: still only 16 bits are being transferred, but the 16 bits from right channel have vanished!

And this is something I neither understand nor having a clue how to resolve it.

over 7 years ago

0 Bob Landers over 7 years ago

TI__Expert 8510 points

I can take a look at this, but it would help to have the rest of the code. Can you send me the main(), or at least a sufficient snippet to replicate what you are trying to do?
Regards,
Bob L.

0 awu@seantec over 7 years ago in reply to Bob Landers

Intellectual 270 points

The main() is from TI-Bluetopia examples, i.e. the A3DPDemo_Sink. I did hook the initialization of the Maxim codec and the DMA stuff into HAL_EnableAudioCodec function. The code is here:

/* DMA Control Table */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(1024)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=1024
#elif defined(__GNUC__)
__attribute__ ((aligned (1024)))
#elif defined(__CC_ARM)
__align(1024)
#endif
static DMA_ControlTable MSP_EXP432P401RLP_DMAControlTable[32];  // from dma_eusci_spi_loopback example

static eUSCI_SPI_MasterConfig spiConfig;

void Init_Maxim(void)
{
   // Switch on master clock generation for Maxim Audio codec
   GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P7, GPIO_PIN0, GPIO_PRIMARY_MODULE_FUNCTION);
   
   fill_buf(audioBuffer);
   fill_buf(audioBuffer + AUDIO_BUFFER_SIZE);
   
   MAP_DMA_enableModule();
   MAP_DMA_setControlBase(MSP_EXP432P401RLP_DMAControlTable);
   
   maximPlayDMAinit(audioBuffer);
   maximStartPlayDMA(); // Will not really start before first trigger occurs

   spiConfig.selectClockSource = EUSCI_B_SPI_CLOCKSOURCE_SMCLK;
   spiConfig.clockSourceFrequency = CS_getSMCLK();   // const
   spiConfig.desiredSpiClock = 3000000UL;  // preliminary maximum
   spiConfig.msbFirst = EUSCI_B_SPI_MSB_FIRST;
   spiConfig.clockPhase = EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT;
   spiConfig.clockPolarity = EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW;
   spiConfig.spiMode = EUSCI_B_SPI_3PIN;

   MAP_SPI_initMaster(EUSCI_B1_BASE, &spiConfig);
   MAP_SPI_enableModule(EUSCI_B1_BASE);
   
   maximInit();   // configure Maxim Audio codec over I2C using EUSCI_B0
   
   maximFramesyncInit();   // Configure TIMER_TA3 for frame sync signal
   
   maximStartSampling();   // Enable counter of TIMER_TA3 - which generates trigger for DMA
}

A few words to the hardware: I attached the module BOOST-CC2564MODA to the TI-MSP-EXP432P401R launchpad, and on top there is my own module with the Audio codec. I made sure that no pins overlap in terms of functionality. The Maxim Codec uses completely different pins than the audio from Bluetooth module.

OT: Why doesn't get the code get highlighted even while I used the "Insert code using Syntaxhighlighter"? For me it does only draw a frame around (in Firefox latest greatest).

0 Bob Landers over 7 years ago in reply to awu@seantec

TI__Expert 8510 points

Can't answer the code highlighting question. I've never seen any actual syntax highlighting- just the gray box and fixed-width text.
-Bob

0 awu@seantec over 7 years ago in reply to Bob Landers

Intellectual 270 points

Meanwhile I did a lot of try and error but it always ends with error. Looking at this thread I think my own description sounds too complicated to me. To keep the things short and better understandable I would summarize my question today in the following way:

I'm using SPI with DMA as in dma_eusci_spi_loopback example from TI. Initialization of DMA channel is:

#define DMA_ARBITRATION_VALUE   UDMA_ARB_2

MAP_DMA_disableChannel(DMA_CHANNEL_6);
MAP_DMA_assignChannel(DMA_CH6_TIMERA3CCR0);
MAP_DMA_disableChannelAttribute(DMA_CH6_TIMERA3CCR0
                                , UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK
                                );
MAP_DMA_setChannelControl(DMA_CH6_TIMERA3CCR0 | UDMA_PRI_SELECT
                      , UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | DMA_ARBITRATION_VALUE
                      );
MAP_DMA_setChannelControl(MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT
                      , UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | DMA_ARBITRATION_VALUE
                      );

If the #define DMA_ARBITRATION_VALUE is either UDMA_ARB_1 or UDMA_ARB_2 the transfer does work as expected, flawlessly.

As soon as I switch to UDMA_ARB_4 it doesn't work well - every 3rd and 4th byte are missing. Why does UDMA_ARB_4 break the functionality?

0 Chris Sterzik over 7 years ago in reply to awu@seantec

TI__Guru 57896 points

multi_channel_02.c

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//*****************************************************************************
//
// Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//  Redistributions of source code must retain the above copyright
//  notice, this list of conditions and the following disclaimer.
//
//  Redistributions in binary form must reproduce the above copyright
//  notice, this list of conditions and the following disclaimer in the
//  documentation and/or other materials provided with the
//  distribution.
//
//  Neither the name of Texas Instruments Incorporated nor the names of
//  its contributors may be used to endorse or promote products derived
//  from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
//*****************************************************************************
//
// MSP432
//
// 4, I2S, 16Bit, 200Khz
//
//
//
// 4, 160us Period Timers: TA0,TA1,TA2,TA3
// 4, 200Khz SPIs: USCA0,USCA1,USCA2,USCA3
// CPU Load: (rising edge processing + falling edge processing)/(total)
//           (  11.54us              +      11.54us           )/160us
//            ~15%
//
//****************************************************************************
#include "msp.h"
/* Standard Includes */
#include <stdint.h>
#include <string.h>
#include <stdbool.h>
/* DriverLib Includes */
#include "driverlib.h"
#define ARRAY_LENGTH    32
#define TRANSMIT_LENGTH 2
/*
 *
 * TA0.1 -> P2.0
 * TA1.1 -> P2.3
 *
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

//*****************************************************************************
//
// Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//  Redistributions of source code must retain the above copyright
//  notice, this list of conditions and the following disclaimer.
//
//  Redistributions in binary form must reproduce the above copyright
//  notice, this list of conditions and the following disclaimer in the
//  documentation and/or other materials provided with the
//  distribution.
//
//  Neither the name of Texas Instruments Incorporated nor the names of
//  its contributors may be used to endorse or promote products derived
//  from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************

//*****************************************************************************
//
// MSP432
//
// 4, I2S, 16Bit, 200Khz
//
//
//
// 4, 160us Period Timers: TA0,TA1,TA2,TA3
// 4, 200Khz SPIs: USCA0,USCA1,USCA2,USCA3
// CPU Load: (rising edge processing + falling edge processing)/(total)
//           (  11.54us              +      11.54us           )/160us
//            ~15%
//
//****************************************************************************

#include "msp.h"
/* Standard Includes */
#include <stdint.h>
#include <string.h>
#include <stdbool.h>

/* DriverLib Includes */
#include "driverlib.h"

#define ARRAY_LENGTH	32
#define TRANSMIT_LENGTH	2

/*
 *
 * TA0.1 -> P2.0
 * TA1.1 -> P2.3
 *
 * USCA0CLK -> P2.1
 * USCA0SIMO -> P2.2
 *
 * USCA1CLK -> P2.4
 * USCA1SIMO -> P2.5
 *
 * USCA2CLK -> P2.6
 * USCA2SIMO -> P2.7
 *
 */
const uint8_t port2_mapping[] =
{
        //Port P2:
	PM_TA0CCR1A, PM_UCA0CLK, PM_UCA0SIMO,
	PM_TA1CCR1A, PM_UCA1CLK, PM_UCA1SIMO,
	PM_UCA2CLK, PM_UCA2SIMO
};

/* SPI Configuration Parameter */
const eUSCI_SPI_MasterConfig spiMasterConfig_A =
{
    EUSCI_A_SPI_CLOCKSOURCE_SMCLK, 3000000, 200000,
    EUSCI_A_SPI_MSB_FIRST,
    EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT,
    EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, EUSCI_A_SPI_3PIN
};
/*
 * Period is 480 SMCLKs, 160us
 */
const Timer_A_UpModeConfig i2s_SEL_CLK_PER =
{
    .clockSource = TIMER_A_CLOCKSOURCE_SMCLK,
    .clockSourceDivider = TIMER_A_CLOCKSOURCE_DIVIDER_1,
    .timerPeriod = 479,
    .timerInterruptEnable_TAIE = TIMER_A_TAIE_INTERRUPT_DISABLE,
    .captureCompareInterruptEnable_CCR0_CCIE = TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE,
    .timerClear = TIMER_A_DO_CLEAR
};

/*
 * Negative Duty Cycle is 240 SMCLKs, 80us
 * Positive Duty Cycle is 480-240 SMCLKs, 80us
 */
const Timer_A_CompareModeConfig i2s_SEL_CLK_DUTY =
{
	.compareInterruptEnable = TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE,
	.compareOutputMode = TIMER_A_OUTPUTMODE_SET_RESET,
	.compareRegister = TIMER_A_CAPTURECOMPARE_REGISTER_1,
	.compareValue 239
};
/*
 * Trigger for Right channel, delayed by one SPI clock cycle
 * 1/200Khz = 5us,  but also reduced to account for ISR
 */
const Timer_A_CompareModeConfig i2s_SEL_CLK_RIGHT =
{
	.compareInterruptEnable = TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE,
	.compareOutputMode = TIMER_A_OUTPUTMODE_SET_RESET,
	.compareRegister = TIMER_A_CAPTURECOMPARE_REGISTER_2,
	.compareValue 247
};

/*
 * Trigger for Left channel, delayed by one SPI clock cycle
 * 1/200Khz = 5us, but also reduced to account for ISR
 */
const Timer_A_CompareModeConfig i2s_SEL_CLK_LEFT =
{
	.compareInterruptEnable = TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE,
	.compareOutputMode = TIMER_A_OUTPUTMODE_SET_RESET,
	.compareRegister = TIMER_A_CAPTURECOMPARE_REGISTER_3,
	.compareValue 448
};

/* DMA Control Table */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(MSP_EXP432P401RLP_DMAControlTable, 1024)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=1024
#elif defined(__GNUC__)
__attribute__ ((aligned (1024)))
#elif defined(__CC_ARM)
__align(1024)
#endif
static DMA_ControlTable MSP_EXP432P401RLP_DMAControlTable[16];  // 8 primary and 8 alternate

/*
 * I2S data, 16 bit, Right and left channels
 */
uint16_t ch0_R[ARRAY_LENGTH];
uint16_t ch0_L[ARRAY_LENGTH];
uint16_t ch1_R[ARRAY_LENGTH];
uint16_t ch1_L[ARRAY_LENGTH];
uint16_t ch2_R[ARRAY_LENGTH];
uint16_t ch2_L[ARRAY_LENGTH];
uint16_t ch3_R[ARRAY_LENGTH];
uint16_t ch3_L[ARRAY_LENGTH];

uint16_t ch0RCnt,ch1RCnt,ch2RCnt,ch3RCnt;
uint16_t ch0LCnt,ch1LCnt,ch2LCnt,ch3LCnt;

void transmitI2S(void);

void main(void)
{
	volatile uint8_t i;
    WDTCTL = WDTPW | WDTHOLD;           // Stop watchdog timer

    /*
     * Init variables for debug
     */
    for(i=0;i<ARRAY_LENGTH/2;i++)
    {
    	ch0_R[2*i] = 0x0180;
    	ch0_L[2*i] = 0x5555;
    	ch0_R[2*i+1] = 0x0180;
    	ch0_L[2*i+1] = 0x5555;

    	ch1_R[2*i] = 0x0180;
    	ch1_L[2*i] = 0x5555;
    	ch1_R[2*i+1] = 0x0180;
    	ch1_L[2*i+1] = 0x5555;

    	ch2_R[2*i] = 0x0180;
    	ch2_L[2*i] = 0x5555;
    	ch2_R[2*i+1] = 0x0180;
    	ch2_L[2*i+1] = 0x5555;

    	ch3_R[2*i] = 0x0180;
    	ch3_L[2*i] = 0x5555;
    	ch3_R[2*i+1] = 0x0180;
    	ch3_L[2*i+1] = 0x5555;
    }

    ch0_L[31] = 0xFFFF;

    /*
     * Debug
     */
    P1OUT &= ~BIT0;
    P1DIR |= BIT0;

    /*
     * Remapping  to P2 and P7
     */
    MAP_PMAP_configurePorts((const uint8_t *) port2_mapping, PMAP_P2MAP, 8,
            PMAP_DISABLE_RECONFIGURATION);
    MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P2,
    		PIN_ALL8, GPIO_PRIMARY_MODULE_FUNCTION);

    /*
     * TA2.1 -> P5.6
     * TA3.1 -> P10.5
     */
    MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P5,GPIO_PIN6,GPIO_PRIMARY_MODULE_FUNCTION);
    MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P10,GPIO_PIN5,GPIO_PRIMARY_MODULE_FUNCTION);
    /*
     * USCA3CLK -> P9.5
     * USCA3SIMO -> P9.7
     */
    MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P9,GPIO_PIN5+GPIO_PIN7,GPIO_PRIMARY_MODULE_FUNCTION);

    /*
     * LDO, Vcore0 (default)
     * 48Mhz MCLK,
     * 3Mhz SMCLK
     */
    MAP_PCM_setPowerState(PCM_AM_LDO_VCORE1);

    MAP_FlashCtl_setWaitState(FLASH_BANK0, 1);
    MAP_FlashCtl_setWaitState(FLASH_BANK1, 1);

    MAP_FlashCtl_enableReadBuffering(FLASH_BANK0,FLASH_INSTRUCTION_FETCH);
    MAP_FlashCtl_enableReadBuffering(FLASH_BANK1,FLASH_INSTRUCTION_FETCH);

    MAP_FlashCtl_enableReadBuffering(FLASH_BANK0,FLASH_DATA_READ);
    MAP_FlashCtl_enableReadBuffering(FLASH_BANK1,FLASH_DATA_READ);
    /* Enabling FPU for DCO Frequency calculation */
    MAP_FPU_enableModule();

    MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
    MAP_CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
    MAP_CS_initClockSignal(CS_SMCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_16);

    /* Configuring SPI module */
    MAP_SPI_initMaster(EUSCI_A0_BASE, &spiMasterConfig_A);
    MAP_SPI_initMaster(EUSCI_A1_BASE, &spiMasterConfig_A);
    MAP_SPI_initMaster(EUSCI_A2_BASE, &spiMasterConfig_A);
    MAP_SPI_initMaster(EUSCI_A3_BASE, &spiMasterConfig_A);

    /* Enable the SPI module */
    MAP_SPI_enableModule(EUSCI_A0_BASE);
    MAP_SPI_enableModule(EUSCI_A1_BASE);
    MAP_SPI_enableModule(EUSCI_A2_BASE);
    MAP_SPI_enableModule(EUSCI_A3_BASE);

    /*
     * Configure TimerA0-A3, PWM with CCR1=CCR2 where CCR1 drives
     * select line and CCR2 drives DMA
     * PER -> period
     * DUTY -> duty cycle (50%)
     * DMA  -> dma trigger, also duty cycle (50%)
     */
    MAP_Timer_A_configureUpMode(TIMER_A0_BASE,&i2s_SEL_CLK_PER);
    MAP_Timer_A_configureUpMode(TIMER_A1_BASE,&i2s_SEL_CLK_PER);
    MAP_Timer_A_configureUpMode(TIMER_A2_BASE,&i2s_SEL_CLK_PER);
    MAP_Timer_A_configureUpMode(TIMER_A3_BASE,&i2s_SEL_CLK_PER);

    MAP_Timer_A_initCompare(TIMER_A0_BASE,&i2s_SEL_CLK_DUTY);
    MAP_Timer_A_initCompare(TIMER_A1_BASE,&i2s_SEL_CLK_DUTY);
    MAP_Timer_A_initCompare(TIMER_A2_BASE,&i2s_SEL_CLK_DUTY);
    MAP_Timer_A_initCompare(TIMER_A3_BASE,&i2s_SEL_CLK_DUTY);

    MAP_Timer_A_initCompare(TIMER_A0_BASE,&i2s_SEL_CLK_RIGHT);
    MAP_Timer_A_initCompare(TIMER_A1_BASE,&i2s_SEL_CLK_RIGHT);
    MAP_Timer_A_initCompare(TIMER_A2_BASE,&i2s_SEL_CLK_RIGHT);
    MAP_Timer_A_initCompare(TIMER_A3_BASE,&i2s_SEL_CLK_RIGHT);

    MAP_Timer_A_initCompare(TIMER_A0_BASE,&i2s_SEL_CLK_LEFT);
    MAP_Timer_A_initCompare(TIMER_A1_BASE,&i2s_SEL_CLK_LEFT);
    MAP_Timer_A_initCompare(TIMER_A2_BASE,&i2s_SEL_CLK_LEFT);
    MAP_Timer_A_initCompare(TIMER_A3_BASE,&i2s_SEL_CLK_LEFT);

    MAP_Interrupt_enableInterrupt(INT_TA0_N);
    MAP_Interrupt_enableInterrupt(INT_TA1_N);
    MAP_Interrupt_enableInterrupt(INT_TA2_N);
    MAP_Interrupt_enableInterrupt(INT_TA3_N);

    MAP_Interrupt_enableMaster();

    ch0RCnt = 0;
    ch1RCnt = 0;
    ch2RCnt = 0;
    ch3RCnt = 0;
    ch0LCnt = 0;
    ch1LCnt = 0;
    ch2LCnt = 0;
    ch3LCnt = 0;

    MAP_Interrupt_enableSleepOnIsrExit();

    MAP_Timer_A_startCounter(TIMER_A0_BASE,TIMER_A_UP_MODE);
    /*
     * Stagger Timers
     */
    __delay_cycles(115);
    MAP_Timer_A_startCounter(TIMER_A1_BASE,TIMER_A_UP_MODE);
    /*
     * Stagger Timers
     */
    __delay_cycles(115);
    MAP_Timer_A_startCounter(TIMER_A2_BASE,TIMER_A_UP_MODE);
    /*
     * Stagger Timers
     */
    __delay_cycles(115);
    MAP_Timer_A_startCounter(TIMER_A3_BASE,TIMER_A_UP_MODE);

    /*
     * Start Timers
     */

    while(1)
    {
        MAP_PCM_gotoLPM0();
        __no_operation();
    }
}

void TA0_N_IRQHandler(void)
{
    if(TIMER_A0->IV == 0x0004)
    {
    	/*
    	 * Transmit data
    	 */
    	//while(!(EUSCI_A0_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A0_SPI->TXBUF = ch0_R[ch0RCnt];
    	while(!(EUSCI_A0_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A0_SPI->TXBUF = (ch0_R[ch0RCnt++] >> 8);
    }
    else
    {
    	//while(!(EUSCI_A0_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A0_SPI->TXBUF = ch0_L[ch0LCnt];
    	while(!(EUSCI_A0_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A0_SPI->TXBUF = (ch0_L[ch0LCnt++] >> 8);
    }
	if(ch0LCnt == ARRAY_LENGTH)
	{
	    ch0RCnt = 0;
	    ch0LCnt = 0;
	}
//    P1OUT ^= BIT0;
}

#if     __TI_COMPILER_VERSION__ >= 15009000
__attribute__((ramfunc))
#endif
void TA1_N_IRQHandler(void)
{
    if(TIMER_A1->IV == 0x0004)
    {
    	/*
    	 * Transmit data
    	 */
    	EUSCI_A1_SPI->TXBUF = ch1_R[ch1RCnt];
    	while(!(EUSCI_A1_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A1_SPI->TXBUF = (ch1_R[ch1RCnt++] >> 8);
    }
    else
    {
    	/*
    	 * Transmit data
    	 */
    	EUSCI_A1_SPI->TXBUF = ch1_L[ch1LCnt];
    	while(!(EUSCI_A1_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A1_SPI->TXBUF = (ch1_L[ch1LCnt++] >> 8);
    }
	if(ch1LCnt == ARRAY_LENGTH)
	{
	    ch1RCnt = 0;
	    ch1LCnt = 0;
	}
//    P1OUT ^= BIT0;
}

void TA2_N_IRQHandler(void)
{
    if(TIMER_A2->IV == 0x0004)
    {
    	/*
    	 * Transmit data
    	 */
    	EUSCI_A2_SPI->TXBUF = (uint8_t)ch2_R[ch2RCnt];
    	while(!(EUSCI_A2_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A2_SPI->TXBUF = (uint8_t)((ch2_R[ch2RCnt++] >> 8) & 0x00FF);
    }
    else
    {
    	/*
    	 * Transmit data
    	 */
    	EUSCI_A2_SPI->TXBUF = (uint8_t)ch2_L[ch2LCnt];
    	while(!(EUSCI_A2_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A2_SPI->TXBUF = (uint8_t)((ch2_L[ch2LCnt++] >> 8) & 0x00FF);
    }
	if(ch2LCnt == ARRAY_LENGTH)
	{
		ch2RCnt = 0;
		ch2LCnt = 0;
	}
}

void TA3_N_IRQHandler(void)
{
    if(TIMER_A3->IV == 0x0004)
    {
    	/*
    	 * Transmit data
    	 */
    	EUSCI_A3_SPI->TXBUF = (uint8_t)ch3_R[ch3RCnt];
    	while(!(EUSCI_A3_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A3_SPI->TXBUF = (uint8_t)((ch3_R[ch3RCnt++] >> 8) & 0x00FF);
    }
    else
    {
    	/*
    	 * Transmit data
    	 */
    	EUSCI_A3_SPI->TXBUF = (uint8_t)ch3_L[ch3LCnt];
    	while(!(EUSCI_A3_SPI->IFG & EUSCI_A_IFG_TXIFG));
    	EUSCI_A3_SPI->TXBUF = (uint8_t)((ch3_L[ch3LCnt++] >> 8) & 0x00FF);
    }
	if(ch3LCnt == ARRAY_LENGTH)
	{
		ch3LCnt = 0;
		ch3RCnt = 0;
	}
//    P1OUT ^= BIT0;
}

I hope this example is of some value.

Chris

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MSP432P401R: 32-Bit DMA over SPI