CCS/EK-TM4C1294XL: Watchdog causing debug problems

Helder Sales

Expert 1220 points

Part Number: EK-TM4C1294XL
Other Parts Discussed in Thread: EK-TM4C123GXL, TM4C1294NCPDT, SEGGER

Tool/software: Code Composer Studio

Hello again,

Now I'm with another EK-TM4C1294XL :D and hopefully this one will last longer.

Anyway, I'm facing a problem, this problem specifically:

CORTEX_M4_0: GEL Output:
Memory Map Initialization Complete
CORTEX_M4_0: Trouble Reading Memory Block at 0x400fe000 on Page 0 of Length 0x4: Debug Port error occurred.
CORTEX_M4_0: Error initializing flash programming: Target failed to read 0x400FE000
CORTEX_M4_0: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.
CORTEX_M4_0: Trouble Writing Register PC: Target is not halted or failed to halt after step.
CORTEX_M4_0: Can't Run Target CPU: Target is not halted or failed to halt after step.
CORTEX_M4_0: Trouble Halting Target CPU

This occurs when I use those functions:

inline void InitWatchdog(void)
{
    ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);
    ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WDOG0);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WDOG1);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG1);
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_WDOG0) || !ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_WDOG1));

    ROM_WatchdogReloadSet(WATCHDOG0_BASE, g_SysClock*0.1);
    ROM_WatchdogReloadSet(WATCHDOG1_BASE, FREQ_PIOSC*0.5);

    ROM_WatchdogResetEnable(WATCHDOG0_BASE);
    ROM_WatchdogResetEnable(WATCHDOG1_BASE);

    ROM_SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG0_SYS);
    ROM_SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG1_SYS);

    ROM_IntDisable(INT_WATCHDOG);
    ROM_IntPendClear(INT_WATCHDOG);
    ROM_WatchdogIntClear(WATCHDOG0_BASE);
    ROM_WatchdogIntClear(WATCHDOG1_BASE);

    ROM_IntPrioritySet(INT_WATCHDOG, 0x00);
    ROM_WatchdogIntEnable(WATCHDOG0_BASE);
    ROM_WatchdogIntEnable(WATCHDOG1_BASE);
    ROM_IntEnable(INT_WATCHDOG);

    ROM_WatchdogEnable(WATCHDOG0_BASE);
    ROM_WatchdogEnable(WATCHDOG1_BASE);

    while(!ROM_WatchdogRunning(WATCHDOG0_BASE) || !ROM_WatchdogRunning(WATCHDOG1_BASE));

    ROM_WatchdogLock(WATCHDOG0_BASE);
    ROM_WatchdogLock(WATCHDOG1_BASE);

    while(!ROM_WatchdogLockState(WATCHDOG0_BASE) || !ROM_WatchdogLockState(WATCHDOG1_BASE));
}

void WatchdogIntHandler(void)
{
    ROM_WatchdogIntClear(WATCHDOG0_BASE);
    ROM_WatchdogIntClear(WATCHDOG1_BASE);
}

On my other Tiva (EK-TM4C123GXL) this code works just fine. Why is that happening?

over 8 years ago

0 Bruno Saraiva over 8 years ago

Guru 13040 points

Good day Helder,

Did you take a look at the memory structure for the specific device of your board? Does that address exist?

There could be a glitch on the Tiva function - not common but not impossible - can you step-into the tiva function and see how the memory address is resolved?

Your new Launchpad will surely last, don't loose your hopes!

Regards

Bruno

0 John Piliounis over 8 years ago

Expert 1690 points

Hello Helder.

a) Omit
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);
b) Use
ROM_WatchdogReloadSet(WATCHDOG0_BASE, g_SysClock/10);
ROM_WatchdogReloadSet(WATCHDOG1_BASE, FREQ_PIOSC/2);
instead of
ROM_WatchdogReloadSet(WATCHDOG0_BASE, g_SysClock*0.1);
ROM_WatchdogReloadSet(WATCHDOG1_BASE, FREQ_PIOSC*0.5);

Run it and tell us.
John

0 Chester Gillon over 8 years ago

Guru 92251 points

Helder Sales said:
CORTEX_M4_0: GEL Output:
Memory Map Initialization Complete
CORTEX_M4_0: Trouble Reading Memory Block at 0x400fe000 on Page 0 of Length 0x4: Debug Port error occurred.
CORTEX_M4_0: Error initializing flash programming: Target failed to read 0x400FE000
CORTEX_M4_0: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.
CORTEX_M4_0: Trouble Writing Register PC: Target is not halted or failed to halt after step.
CORTEX_M4_0: Can't Run Target CPU: Target is not halted or failed to halt after step.
CORTEX_M4_0: Trouble Halting Target CPU

Do those errors occur when starting a debug session, when the EK-TM4C1294XL already contains a program which has enabled the watchdog?

If so an enabled watchdog may be resetting the device during the flash programming that occurs when CCS downloads a new program at the start of debug session.

Under the CCS project properties there are options you can set to perform a reset during a download which should disable an active watchdog, under both:

- Debug -> Program/Memory Load Options -> Connection Options -> Reset the target on a connect

- Debug -> Flash Settings -> Flash Settings -> Reset target during program load to Flash memory

Try setting those options to reset the target.

Note that there is a bug in CCS 7.0 and CCS 7.1 where attempting to set the "Reset the target on a connect" and "Reset target during program load to Flash memory" options has no effect (https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/589281). A work-around is to the add the following to the GEL script for the device:

OnPreFileLoaded()
{
    GEL_AdvancedReset ("System Reset");
}

Helder Sales said:
On my other Tiva (EK-TM4C123GXL) this code works just fine. Why is that happening?

The EK-TM4C123GXL has less flash than the EK-TM4C1294XL, so maybe a watchdog reset is less likely to occur during the flash programming.

0 Charles Tsai over 8 years ago

TI__Guru**** 191906 points

Hi Helder,
Do you already have the code loaded into the flash before seeing the error message? Please also check when you setup your target configuration make sure you select the device that matches the one on the EK LaunchPad. if the code is already running then I feel that the watchdog reset might have prevented the debugger from connecting.

0 Helder Sales over 8 years ago in reply to Charles Tsai

Expert 1220 points

Hello all,

I've confirmed that the Watchdog reset is the cause of the problem. But I'm not sure how to proceed with the GEL file (never worked with that).

I've opened tm4c1294ncpdt.gel and placed the lines that Chester's mentioned, but the problem still remains.

The code inside the file looks like that:

/* tm4c1294ncpdt.gel
 *
 * Revisions:
 *  June-10-2014 3rd revision
 *
 * This is derived from revision 15071 of the TivaWare Library.
 *
 */

OnPreFileLoaded()
{
    GEL_AdvancedReset ("System Reset");
}

menuitem "StartUp"

hotmenu StartUp()
{
    /* Load the CortexM3_util.gel file */
    GEL_LoadGel("$(GEL_file_dir)/CortexM3_util.gel");

    GEL_MapOff();
    GEL_MapReset();
    GEL_MapOn();
    memorymap_init();
}

OnTargetConnect()
{
}

memorymap_init()
{
    /*
     * Syntax for GEL_MapAddStr.
     * GEL_MapAddStr(address, page, length, "attribute", waitstate);

    Basic Attribute Types           Derived Attribute Types
    String      Description         String      Description
    R           Read                NONE        No memory/protected
    W           Write               RAM         Read and write
    P           Port                ROM         Read only
    EX          External            WOM         Write only
    EM          Emulator            INPORT      Port read only
    PR          Programmable        OUTPORT     Port write only
    ER          Erasable            IOPORT      Port read and write
    DA          Dual access         SARAM       Single access RAM
    ASn         Access size         DARAM       Dual access RAM
    SHnC        Shared              FLASH       Flash ROM
    CACHE       Cache               EXRAM       External RAM
    TX          Text                EXROM       External ROM
    MN          Monitor             EPROM       Erasable write-able EPROM
    SA          Single access       MONITOR     Monitor ROM
    FL          Flash               PRAM        Program RAM
    MR          Memory mapped       PROM        Program ROM
    NULL        NULL                NULL        NULL

    */

    GEL_MapAddStr(0x00000000, 0, 0x00100000, "R", 0);  /* Flash */
    GEL_MapAddStr(0x01000000, 0, 0x00008c00, "R", 0);  /* ROM */
    GEL_MapAddStr(0x20000000, 0, 0x00040000, "R|W", 0);  /* SRAM */
    GEL_MapAddStr(0x40000000, 0, 0x00001000, "R|W", 0);  /* WATCHDOG0 */
    GEL_MapAddStr(0x40001000, 0, 0x00001000, "R|W", 0);  /* WATCHDOG1 */
    GEL_MapAddStr(0x40008000, 0, 0x00001000, "R|W", 0);  /* SSI0 */
    GEL_MapAddStr(0x40009000, 0, 0x00001000, "R|W", 0);  /* SSI1 */
    GEL_MapAddStr(0x4000A000, 0, 0x00001000, "R|W", 0);  /* SSI2 */
    GEL_MapAddStr(0x4000B000, 0, 0x00001000, "R|W", 0);  /* SSI3 */
    GEL_MapAddStr(0x4000C000, 0, 0x00001000, "R|W", 0);  /* UART0 */
    GEL_MapAddStr(0x4000D000, 0, 0x00001000, "R|W", 0);  /* UART1 */
    GEL_MapAddStr(0x4000E000, 0, 0x00001000, "R|W", 0);  /* UART2 */
    GEL_MapAddStr(0x4000F000, 0, 0x00001000, "R|W", 0);  /* UART3 */
    GEL_MapAddStr(0x40010000, 0, 0x00001000, "R|W", 0);  /* UART4 */
    GEL_MapAddStr(0x40011000, 0, 0x00001000, "R|W", 0);  /* UART5 */
    GEL_MapAddStr(0x40012000, 0, 0x00001000, "R|W", 0);  /* UART6 */
    GEL_MapAddStr(0x40013000, 0, 0x00001000, "R|W", 0);  /* UART7 */
    GEL_MapAddStr(0x40020000, 0, 0x00001000, "R|W", 0);  /* I2C0 */
    GEL_MapAddStr(0x40021000, 0, 0x00001000, "R|W", 0);  /* I2C1 */
    GEL_MapAddStr(0x40022000, 0, 0x00001000, "R|W", 0);  /* I2C2 */
    GEL_MapAddStr(0x40023000, 0, 0x00001000, "R|W", 0);  /* I2C3 */
    GEL_MapAddStr(0x40028000, 0, 0x00001000, "R|W", 0);  /* PWM0 */
    GEL_MapAddStr(0x4002C000, 0, 0x00001000, "R|W", 0);  /* QEI0 */
    GEL_MapAddStr(0x40030000, 0, 0x00001000, "R|W", 0);  /* TIMER0 */
    GEL_MapAddStr(0x40031000, 0, 0x00001000, "R|W", 0);  /* TIMER1 */
    GEL_MapAddStr(0x40032000, 0, 0x00001000, "R|W", 0);  /* TIMER2 */
    GEL_MapAddStr(0x40033000, 0, 0x00001000, "R|W", 0);  /* TIMER3 */
    GEL_MapAddStr(0x40034000, 0, 0x00001000, "R|W", 0);  /* TIMER4 */
    GEL_MapAddStr(0x40035000, 0, 0x00001000, "R|W", 0);  /* TIMER5 */
    GEL_MapAddStr(0x40038000, 0, 0x00001000, "R|W", 0);  /* ADC0 */
    GEL_MapAddStr(0x40039000, 0, 0x00001000, "R|W", 0);  /* ADC1 */
    GEL_MapAddStr(0x4003C000, 0, 0x00001000, "R|W", 0);  /* COMP */
    GEL_MapAddStr(0x40040000, 0, 0x00001000, "R|W", 0);  /* CAN0 */
    GEL_MapAddStr(0x40041000, 0, 0x00001000, "R|W", 0);  /* CAN1 */
    GEL_MapAddStr(0x40050000, 0, 0x00001000, "R|W", 0);  /* USB0 */
    GEL_MapAddStr(0x40058000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTA AHB */
    GEL_MapAddStr(0x40059000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTB AHB */
    GEL_MapAddStr(0x4005A000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTC AHB */
    GEL_MapAddStr(0x4005B000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTD AHB */
    GEL_MapAddStr(0x4005C000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTE AHB */
    GEL_MapAddStr(0x4005D000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTF AHB */
    GEL_MapAddStr(0x4005E000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTG AHB */
    GEL_MapAddStr(0x4005F000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTH AHB */
    GEL_MapAddStr(0x40060000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTJ AHB */
    GEL_MapAddStr(0x40061000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTK */
    GEL_MapAddStr(0x40062000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTL */
    GEL_MapAddStr(0x40063000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTM */
    GEL_MapAddStr(0x40064000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTN */
    GEL_MapAddStr(0x40065000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTP */
    GEL_MapAddStr(0x40066000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTQ */
    GEL_MapAddStr(0x400AF000, 0, 0x00001000, "R|W", 0);  /* EEPROM */
    GEL_MapAddStr(0x400B8000, 0, 0x00001000, "R|W", 0);  /* I2C8 */
    GEL_MapAddStr(0x400B9000, 0, 0x00001000, "R|W", 0);  /* I2C9 */
    GEL_MapAddStr(0x400C0000, 0, 0x00001000, "R|W", 0);  /* I2C4 */
    GEL_MapAddStr(0x400C1000, 0, 0x00001000, "R|W", 0);  /* I2C5 */
    GEL_MapAddStr(0x400C2000, 0, 0x00001000, "R|W", 0);  /* I2C6 */
    GEL_MapAddStr(0x400C3000, 0, 0x00001000, "R|W", 0);  /* I2C7 */
    GEL_MapAddStr(0x400D0000, 0, 0x00001000, "R|W", 0);  /* EPI0 */
    GEL_MapAddStr(0x400E0000, 0, 0x00001000, "R|W", 0);  /* TIMER6 */
    GEL_MapAddStr(0x400E1000, 0, 0x00001000, "R|W", 0);  /* TIMER7 */
    GEL_MapAddStr(0x400EC000, 0, 0x00001000, "R|W", 0);  /* EMAC0 */
    GEL_MapAddStr(0x400F9000, 0, 0x00001000, "R|W", 0);  /* SYSEXC */
    GEL_MapAddStr(0x400FC000, 0, 0x00001000, "R|W", 0);  /* HIB */
    GEL_MapAddStr(0x400FD000, 0, 0x00001000, "R|W", 0);  /* FLASH CTRL */
    GEL_MapAddStr(0x400FE000, 0, 0x00001000, "R|W", 0);  /* SYSCTL */
    GEL_MapAddStr(0x400FF000, 0, 0x00001000, "R|W", 0);  /* UDMA */
    GEL_MapAddStr(0x44030000, 0, 0x00001000, "R|W", 0);  /* CCM0 */
    GEL_MapAddStr(0xE000E000, 0, 0x00001000, "R|W", 0);  /* NVIC */

    GEL_TextOut("\nMemory Map Initialization Complete\n");

}

I also attemped to modify CortexM3_util.gel, without sucess.

/*******************************************************************/ 
/* This GEL file is loaded on the command line of Code Composer    */
/*                                                                 */
/* History:                                                        */
/* Version  Author         Date        Comments                    */
/* 1.0      Kamal Nehal    Unknown     Initial Version AEC/Aries   */
/* 1.1      Krishna Allam  11/30/2009  Removed use of GEL_WatchAdd */
/*                                     It is not supported in CCSv4*/
/*******************************************************************/

OnPreFileLoaded()
{
    GEL_AdvancedReset ("System Reset");
}

#define MPU_ON    0x00000001
#define MPU_OFF   ~MPU_ON


menuitem "MPU"

hotmenu Enable_MPU()
{
   int status;

    status =  MPU_CONTROL;
    status |= MPU_ON;
    MPU_CONTROL = status;

    status = MPU_CONTROL;

    if ( (status & MPU_ON) == MPU_ON )
    {
        GEL_TextOut("MPU is ON. \n\n");
    }
   else
   {
       GEL_TextOut("MPU is OFF. \n\n");
   }
}

hotmenu Disable_MPU()
{
    int status;

    status =  MPU_CONTROL;
    status &= MPU_OFF;
    MPU_CONTROL= status;

    status = MPU_CONTROL;

    if ( (status & MPU_ON) == MPU_ON )
    {
        GEL_TextOut("MPU Is ON. \n\n");
    }
    else
    {
       GEL_TextOut("MPU Is OFF. \n\n");
    }
}

Well, Tiva is an ARM Cortex-M4F device, why the GEL file is Cortex_M3?

0 Bruno Saraiva over 8 years ago in reply to Helder Sales

Guru 13040 points

I know nothing about GEL - or any other hair styling products for what it is worth. But would it work if you enable the watchdog as late as possible into your initialization process, just before the main loop?

0 Chester Gillon over 8 years ago in reply to Helder Sales

Guru 92251 points

Helder Sales said:
I've opened tm4c1294ncpdt.gel and placed the lines that Chester's mentioned, but the problem still remains.

I omitted to mention it, but CCS has a separate General Extension Language GEL file for each Tiva device, and the GEL file is specified in the Target Configuration File (.ccxml) file for the project. On creating a new target configuration for a Tiva device CCS will default to select the GEL file for that device in the CCS installation. However, the user may change the GEL file used.

If you look in the GEL Files view in the CCS debugger and hover the cursor over a file name, CCS will report the absolute path of the GEL file in use so you can confirm the correct file has been changed:

Helder Sales said:
I also attemped to modify CortexM3_util.gel, without sucess.

You should only need to add the OnPreFileLoaded() function to the tm4c1294ncpdt.gel device GEL file or the CortexM3_util.gel utility GEL file, and if you change both files then expect you will get an error that the OnPreFileLoaded() function has been defined twice. Since CortexM3_util.gel gets referenced by a number of Cortex M3/M4/M4F device GEL files recommend that leave CortexM3_util.gel unchanged.

Helder Sales said:
Well, Tiva is an ARM Cortex-M4F device, why the GEL file is Cortex_M3?

A Cortex M4F is a super-set of a Cortex-M3 device, which is why I think the CortexM3_util.gel utility also gets used by some Cortex-M4F device GEL files.

0 Helder Sales over 8 years ago in reply to Bruno Saraiva

Expert 1220 points

Bruno Saraiva said:
I know nothing about GEL - or any other hair styling products for what it is worth. But would it work if you enable the watchdog as late as possible into your initialization process, just before the main loop?

Yes, I suppose. A good alternative until they fix the bug in the debugger. But I'm open for suggestions about the GEL file (not the hairstyling products heh).

0 Bruno Saraiva over 8 years ago in reply to Helder Sales

Guru 13040 points

Helder Sales said:
the bug in the debugger

That's when all hope for mankind is gone...

0 Helder Sales over 8 years ago in reply to Chester Gillon

Expert 1220 points

Chester Gillon said:

If you look in the GEL Files view in the CCS debugger and hover the cursor over a file name, CCS will report the absolute path of the GEL file in use so you can confirm the correct file has been changed:

I tried to insert the OnPreFileLoaded() function in both files, one at a time like you suggested, but Watchdog is still interfering in the debug process.

0 Chester Gillon over 8 years ago in reply to Helder Sales

Guru 92251 points

Helder Sales said:
I tried to insert the OnPreFileLoaded() function in both files, one at a time like you suggested, but Watchdog is still interfering in the debug process.

If you move the GEL_AdvancedReset ("System Reset"); call from the OnPreFileLoaded() to OnTargetConnect() GEL function does that fix the problem?

This is a guess that moving the System Reset to sooner in the debug start-up might help.

If that doesn't prevent the Watchdog from interfering in the debug process, will attempt to investigate.

0 Helder Sales over 8 years ago in reply to Chester Gillon

Expert 1220 points

Unfortunately, didn't work. Another error kicks in:

CORTEX_M4_0: GEL Output:

Memory Map Initialization Complete

CORTEX_M4_0: Error

CORTEX_M4_0: Error: Timed out while waiting for target powerup/polling a hardware resource.

0 Chester Gillon over 8 years ago in reply to Helder Sales

Guru 92251 points

Helder Sales said:
Unfortunately, didn't work. Another error kicks in:

OK, remove the suggested GEL_AdvancedReset from the GEL files.

I have just remembered that another user had previously come-up with a different solution, which was to modify the GEL files to write to the watchdog registers to disable the watchdog - see https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/286801/1092105#1092105

0 Helder Sales over 8 years ago in reply to Chester Gillon

Expert 1220 points

Chester Gillon said:

I have just remembered that another user had previously come-up with a different solution, which was to modify the GEL files to write to the watchdog registers to disable the watchdog - see https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/286801/1092105#1092105

Seems a good solution, but how do I proceed exactly? If I paste the code on the GEL file, it has no effect.

/* tm4c1294ncpdt.gel
 *
 * Revisions:
 *  June-10-2014 3rd revision
 *
 * This is derived from revision 15071 of the TivaWare Library.
 *
 */

// Disable WATCHDOG0 and WATCHDOG1 modules prior to loading a file, so that
// the watchdog doesn't corrupt downloading to flash
#define WDOG0_BASE 0x40000000
#define WDOG1_BASE 0x40001000
#define WDOG_O_LOCK 0x0C00
#define WDOG_O_CTL 0x0008

#define SYSCTL_RCGCWD 0x400FE600

#define WR_MEM_32(addr, data) *(unsigned int*)(addr) = (unsigned int)(data)
#define RD_MEM_32(addr) *(unsigned int*)(addr)

OnPreFileLoaded()
{
if(RD_MEM_32(SYSCTL_RCGCWD) & 0x00000001)
{
// Watchdog0 is being used (clock is enabled)

//Unlock the watchdog register
WR_MEM_32 (WDOG0_BASE + WDOG_O_LOCK, 0x1ACCE551);

//Clear the watchdog reset enable flag
WR_MEM_32 (WDOG0_BASE + WDOG_O_CTL, RD_MEM_32(WDOG0_BASE + WDOG_O_CTL) & 0xFFFFFFFD);

//Re-Lock the watchdog register
WR_MEM_32 (WDOG0_BASE + WDOG_O_LOCK, 0x00000001);
}

if(RD_MEM_32(SYSCTL_RCGCWD) & 0x00000002)
{
// Watchdog1 is being used (clock is enabled)

//Unlock the watchdog register
WR_MEM_32 (WDOG1_BASE + WDOG_O_LOCK, 0x1ACCE551);

//Clear the watchdog reset enable flag
WR_MEM_32 (WDOG1_BASE + WDOG_O_CTL, RD_MEM_32(WDOG1_BASE + WDOG_O_CTL) & 0xFFFFFFFD);

//Re-Lock the watchdog register
WR_MEM_32 (WDOG1_BASE + WDOG_O_LOCK, 0x00000001);
}
}

menuitem "StartUp"

hotmenu StartUp()
{
    /* Load the CortexM3_util.gel file */
    GEL_LoadGel("$(GEL_file_dir)/CortexM3_util.gel");

    GEL_MapOff();
    GEL_MapReset();
    GEL_MapOn();
    memorymap_init();
}

OnTargetConnect()
{
}

memorymap_init()
{
    /*
     * Syntax for GEL_MapAddStr.
     * GEL_MapAddStr(address, page, length, "attribute", waitstate);

    Basic Attribute Types           Derived Attribute Types
    String      Description         String      Description
    R           Read                NONE        No memory/protected
    W           Write               RAM         Read and write
    P           Port                ROM         Read only
    EX          External            WOM         Write only
    EM          Emulator            INPORT      Port read only
    PR          Programmable        OUTPORT     Port write only
    ER          Erasable            IOPORT      Port read and write
    DA          Dual access         SARAM       Single access RAM
    ASn         Access size         DARAM       Dual access RAM
    SHnC        Shared              FLASH       Flash ROM
    CACHE       Cache               EXRAM       External RAM
    TX          Text                EXROM       External ROM
    MN          Monitor             EPROM       Erasable write-able EPROM
    SA          Single access       MONITOR     Monitor ROM
    FL          Flash               PRAM        Program RAM
    MR          Memory mapped       PROM        Program ROM
    NULL        NULL                NULL        NULL

    */

    GEL_MapAddStr(0x00000000, 0, 0x00100000, "R", 0);  /* Flash */
    GEL_MapAddStr(0x01000000, 0, 0x00008c00, "R", 0);  /* ROM */
    GEL_MapAddStr(0x20000000, 0, 0x00040000, "R|W", 0);  /* SRAM */
    GEL_MapAddStr(0x40000000, 0, 0x00001000, "R|W", 0);  /* WATCHDOG0 */
    GEL_MapAddStr(0x40001000, 0, 0x00001000, "R|W", 0);  /* WATCHDOG1 */
    GEL_MapAddStr(0x40008000, 0, 0x00001000, "R|W", 0);  /* SSI0 */
    GEL_MapAddStr(0x40009000, 0, 0x00001000, "R|W", 0);  /* SSI1 */
    GEL_MapAddStr(0x4000A000, 0, 0x00001000, "R|W", 0);  /* SSI2 */
    GEL_MapAddStr(0x4000B000, 0, 0x00001000, "R|W", 0);  /* SSI3 */
    GEL_MapAddStr(0x4000C000, 0, 0x00001000, "R|W", 0);  /* UART0 */
    GEL_MapAddStr(0x4000D000, 0, 0x00001000, "R|W", 0);  /* UART1 */
    GEL_MapAddStr(0x4000E000, 0, 0x00001000, "R|W", 0);  /* UART2 */
    GEL_MapAddStr(0x4000F000, 0, 0x00001000, "R|W", 0);  /* UART3 */
    GEL_MapAddStr(0x40010000, 0, 0x00001000, "R|W", 0);  /* UART4 */
    GEL_MapAddStr(0x40011000, 0, 0x00001000, "R|W", 0);  /* UART5 */
    GEL_MapAddStr(0x40012000, 0, 0x00001000, "R|W", 0);  /* UART6 */
    GEL_MapAddStr(0x40013000, 0, 0x00001000, "R|W", 0);  /* UART7 */
    GEL_MapAddStr(0x40020000, 0, 0x00001000, "R|W", 0);  /* I2C0 */
    GEL_MapAddStr(0x40021000, 0, 0x00001000, "R|W", 0);  /* I2C1 */
    GEL_MapAddStr(0x40022000, 0, 0x00001000, "R|W", 0);  /* I2C2 */
    GEL_MapAddStr(0x40023000, 0, 0x00001000, "R|W", 0);  /* I2C3 */
    GEL_MapAddStr(0x40028000, 0, 0x00001000, "R|W", 0);  /* PWM0 */
    GEL_MapAddStr(0x4002C000, 0, 0x00001000, "R|W", 0);  /* QEI0 */
    GEL_MapAddStr(0x40030000, 0, 0x00001000, "R|W", 0);  /* TIMER0 */
    GEL_MapAddStr(0x40031000, 0, 0x00001000, "R|W", 0);  /* TIMER1 */
    GEL_MapAddStr(0x40032000, 0, 0x00001000, "R|W", 0);  /* TIMER2 */
    GEL_MapAddStr(0x40033000, 0, 0x00001000, "R|W", 0);  /* TIMER3 */
    GEL_MapAddStr(0x40034000, 0, 0x00001000, "R|W", 0);  /* TIMER4 */
    GEL_MapAddStr(0x40035000, 0, 0x00001000, "R|W", 0);  /* TIMER5 */
    GEL_MapAddStr(0x40038000, 0, 0x00001000, "R|W", 0);  /* ADC0 */
    GEL_MapAddStr(0x40039000, 0, 0x00001000, "R|W", 0);  /* ADC1 */
    GEL_MapAddStr(0x4003C000, 0, 0x00001000, "R|W", 0);  /* COMP */
    GEL_MapAddStr(0x40040000, 0, 0x00001000, "R|W", 0);  /* CAN0 */
    GEL_MapAddStr(0x40041000, 0, 0x00001000, "R|W", 0);  /* CAN1 */
    GEL_MapAddStr(0x40050000, 0, 0x00001000, "R|W", 0);  /* USB0 */
    GEL_MapAddStr(0x40058000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTA AHB */
    GEL_MapAddStr(0x40059000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTB AHB */
    GEL_MapAddStr(0x4005A000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTC AHB */
    GEL_MapAddStr(0x4005B000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTD AHB */
    GEL_MapAddStr(0x4005C000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTE AHB */
    GEL_MapAddStr(0x4005D000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTF AHB */
    GEL_MapAddStr(0x4005E000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTG AHB */
    GEL_MapAddStr(0x4005F000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTH AHB */
    GEL_MapAddStr(0x40060000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTJ AHB */
    GEL_MapAddStr(0x40061000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTK */
    GEL_MapAddStr(0x40062000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTL */
    GEL_MapAddStr(0x40063000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTM */
    GEL_MapAddStr(0x40064000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTN */
    GEL_MapAddStr(0x40065000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTP */
    GEL_MapAddStr(0x40066000, 0, 0x00001000, "R|W", 0);  /* GPIO PORTQ */
    GEL_MapAddStr(0x400AF000, 0, 0x00001000, "R|W", 0);  /* EEPROM */
    GEL_MapAddStr(0x400B8000, 0, 0x00001000, "R|W", 0);  /* I2C8 */
    GEL_MapAddStr(0x400B9000, 0, 0x00001000, "R|W", 0);  /* I2C9 */
    GEL_MapAddStr(0x400C0000, 0, 0x00001000, "R|W", 0);  /* I2C4 */
    GEL_MapAddStr(0x400C1000, 0, 0x00001000, "R|W", 0);  /* I2C5 */
    GEL_MapAddStr(0x400C2000, 0, 0x00001000, "R|W", 0);  /* I2C6 */
    GEL_MapAddStr(0x400C3000, 0, 0x00001000, "R|W", 0);  /* I2C7 */
    GEL_MapAddStr(0x400D0000, 0, 0x00001000, "R|W", 0);  /* EPI0 */
    GEL_MapAddStr(0x400E0000, 0, 0x00001000, "R|W", 0);  /* TIMER6 */
    GEL_MapAddStr(0x400E1000, 0, 0x00001000, "R|W", 0);  /* TIMER7 */
    GEL_MapAddStr(0x400EC000, 0, 0x00001000, "R|W", 0);  /* EMAC0 */
    GEL_MapAddStr(0x400F9000, 0, 0x00001000, "R|W", 0);  /* SYSEXC */
    GEL_MapAddStr(0x400FC000, 0, 0x00001000, "R|W", 0);  /* HIB */
    GEL_MapAddStr(0x400FD000, 0, 0x00001000, "R|W", 0);  /* FLASH CTRL */
    GEL_MapAddStr(0x400FE000, 0, 0x00001000, "R|W", 0);  /* SYSCTL */
    GEL_MapAddStr(0x400FF000, 0, 0x00001000, "R|W", 0);  /* UDMA */
    GEL_MapAddStr(0x44030000, 0, 0x00001000, "R|W", 0);  /* CCM0 */
    GEL_MapAddStr(0xE000E000, 0, 0x00001000, "R|W", 0);  /* NVIC */

    GEL_TextOut("\nMemory Map Initialization Complete\n");

}

0 Charles Tsai over 8 years ago in reply to Helder Sales

TI__Guru**** 191906 points

What you want to try is to halt the CPU before it enables the watchdog code. Try to hold the reset button and connect to the target right after you release the reset button. If you are fast enough you may be able to halt the CPU before the WD is enabled. You probably need to try quite a few times to see if you can get this to work. Once connected you can then erase the flash.

0 Chester Gillon over 8 years ago in reply to Helder Sales

Guru 92251 points

Helder Sales said:
Seems a good solution, but how do I proceed exactly? If I paste the code on the GEL file, it has no effect.

I copied your watchdog initialization code into a program for a EK-TM4C1294XL, so I could investigate the GEL file changes.

However, once I had loaded the program into the EK-TM4C1294XL such that the watchdog was enabled, further attempts to download using CCS 7.1 and the on-board Stellaris ICDI resulted in CCS becoming non-responsive such that had to kill CCS with the Windows task manager.

Then switched to using a Segger J-Link. Using the original CCS 7.1 tm4c1294ncpdt.gel GEL file with the Segger J-Link showed that that the EK-TM4C1294XL with the watchdog enabled also caused the Segger J-Link flash programming to fail when trying to start a debug session:

CORTEX_M4_0: GEL Output:
Memory Map Initialization Complete
CORTEX_M4_0: Trouble Writing Register PC: Timeout while checking target RAM, RAMCode did not respond in time Failed to prepare for programming. Failed to execute RAMCode for RAM check! Can not read register 20 (CFBP) while CPU is runningCPU is not halted

I then tried changes to the tm4c1294ncpdt.gel GEL file to disable the watchdogs when connecting to the target. Ended up with the GEL script reseting and then disabling the watchdogs if they were enabled. Text is reported to the debugger console to indicate when the watchdogs are being disabled. E.g.:

CORTEX_M4_0: GEL Output:
Memory Map Initialization Complete
CORTEX_M4_0: GEL Output: OnTargetConnect
CORTEX_M4_0: GEL Output: Disabling Watchdog0
CORTEX_M4_0: GEL Output: Disabling Watchdog1
CORTEX_M4_0: GEL Output: OnPreFileLoaded

With the changed tm4c1294ncpdt.gel GEL file CCS 7.1 with a Segger J-Link could reliable start a debug session when the program in the EK-TM4C1294XL had enabled the watchdog.

However, when went to try the changed tm4c1294ncpdt.gel GEL file with CCS 7.1 and a Stellaris ICDI, CCS 7.1 went back to locking up when starting a debug session.

Having used the Segger J-Link to load a program which didn't enable the watchdog, was then able again to use CCS 7.1 and the Stellaris ICDI to load programs.

I have attached the modified tm4c1294ncpdt.gel GEL file which was successful with the Segger J-Link, in case it works for you with a Stellaris ICDI.

tm4c1294ncpdt.zip

LM Flash Programmer was able to perform an unlock using the Stellaris ICDI to recover the EK-TM4C1294XL when the program had enabled the watchdog, so maybe that is option for you.

0 Helder Sales over 8 years ago in reply to Chester Gillon

Expert 1220 points

It worked one time only. I think I'll use the LM Flash Programmer for now. But thank you for all the time you spent trying to solve the issue, I really do appreciate, and the other's suggestions as well.

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CCS/EK-TM4C1294XL: Watchdog causing debug problems